This paper presents a fast transient LDO with high power supply rejection ratio (PSRR) over 100-kHz based on adaptive biasing, dynamic biasing technique and a current mode feed-forward amplifier (CMFFA). The dynamic biasing improves the load transient response and the adaptive biasing benefits the loop stability. The CMFFA introduces a left-half-plane zero to compensate for the non-dominant pole without large current consumption. Moreover, a impedance adaptive circuit is also used in this design: it ensures the DC gain and pushes a nondominant pole to high frequency. Through these methods, the proposed LDO is stable over full load range, from 0mA to 150mA, it achieves fast transient response and high PSRR with a low quiescent current. The LDO is fabricated in a 0.6-μm CMOS technology. The output voltage can be regulated from 1.8V to 3.3V and the load capacitance is 1 μF. For a 150mA load step and a 3.3V output voltage, the maximum undershoot voltage is 38.6mV. At maximum load condition, a 41dB PSRR is achieved at 100-kHz and the loop gain bandwidth product is 1.9MHz. The DC gain is around 70dB over the full load range. The measured load regulation and line regulation are 0.06mV/mA and 1mV/V, respectively. The LDO has a minimum quiescent current of 9.6μA without load. Finally, the proposed LDO achieves a FOM1 of 16.47ps and a FOM2 of 123.52μV.

This article presents a fast-transient radiation-hardened low-dropout (LDO) voltage regulator integrated in a standard 0.6-μm BiCMOS technology for space and other harsh radiation environment applications. The fabricated LDO consumes 150- μA quiescent current at 6-A maximum output current. An LDO voltage of 300 mV which corresponds to an ultralow R _DS(ON) resistance of 500 mΩ is realized by accurate modeling. A separate fast-transient response circuit under narrow-bandwidth condition is proposed to improve the output voltage transient speed. It operates from an input voltage range of 2.8-5.5 V and provides an output voltage of 2.5 V, with output voltage accuracy of ±2%. The proposed LDO achieves a successful line regulation of 1 mV/V, and a load regulation of 2.16 mV/A. Effective radiation-hardened layout techniques are applied to realize high area-efficient LDO chip, whose total area including pads is 5.35 mm ² , which represents only about one-third area of similar radiation-hardened products. Furthermore, a special set of total ionizing dose (TID) experiments and single-event latch-up (SEL) experiments were performed. The measurement results show that the LDO can tolerate up to a TID of 150 krad (Si) and SEL immunity at a linear energy transfer (LET) of 99.8 MeV/(mg/cm ² ) with proposed layout design.

This paper presents a high precision adaptive slope compensation circuit for for DC-DC converter in wearable devices. Compared with the traditional adaptive slope compensation circuit, the comparator is used to sample the output voltage and input voltage, which greatly improves the accuracy.In this paper, the circuit is designed in UMC 0.18-μm CMOS Technology and verified by Virtuoso Spectre Circuit Simulator. The simulation results show that the accuracy of the adaptive slope compensation circuit in this paper can reach more than 96%.