Continuous developments in the electronics industry have led to constantly changing career roles and graduate skills requirements. Students in the University of Electronic Science and Technology of China (UESTC) have complained that numerous courses in electronic engineering are heavily focused on theoretical knowledge that is disconnected from the needs of the industry. Thus, in an effort toward delivering student-centered educational programmes that meet the needs of the industry, this article introduces an innovative course that was developed using the project-based learning (PBL) method and situated in the electronic engineering undergraduate programme at UESTC. Since real-world engineering projects require teams to collaborate on ill-defined problems, we focused this innovative course on developing professional and technical skills, drawing from a range of more typical electronic engineering courses. We provide full details of two projects that were created for this PBL approach and evaluate them as practice examples that demonstrate the impact of this practical pedagogic innovation in UESTC. According to our evaluation, completed by all 40 of our enrolled students, our innovative course based on interdisciplinary PBL exercises demonstrated a significant improvement in student satisfaction and 65% of students preferred the interdisciplinary PBL course in comparison to traditional lecture-based courses.

This paper presents a circuit design and an implementation of a four-channel 12-bit digital-to-analog converter (DAC) with high-voltage operation and radiation-tolerant attribute using a specific CSMC H8312 0.5-μm Bi-CMOS technology to achieve the functionality across a wide-temperature range from -55 °C to 125 °C. In this paper, an R-2R resistor network is adopted in the DAC to provide necessary resistors matching which improves the DAC precision and linearity with both the global common centroid and local common centroid layout. Therefore, no additional, complicated digital calibration or laser-trimming are needed in this design. The experimental and measurement results show that the maximum frequency of the single-chip four-channel 12-bit R-2R ladder high-voltage radiation-tolerant DAC is 100 kHz, and the designed DAC achieves the maximum value of differential non-linearity of 0.18 LSB, and the maximum value of integral non-linearity of -0.53 LSB at 125 °C, which is close to the optimal DAC performance. The performance of the proposed DAC keeps constant over the whole temperature range from -55 °C to 125 °C. Furthermore, an enhanced radiation-hardened design has been demonstrated by utilizing a radiation chamber experimental setup. The fabricated radiation-tolerant DAC chipset occupies a die area of 7 mm × 7 mm in total including pads (core active area of 4 mm × 5 mm excluding pads) and consumes less than 525 mW, output voltage ranges from -10 to +10 V.

This brief proposes two digital-to-analog converter switching techniques for binary-weighted capacitor array successive approximation register (SAR) analog-to-digital converter (ADC), rotating&averaging without redundancy technique and rotating&averaging with redundancy technique. The rotating&averaging without redundancy technique can improve the signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) of conventional SAR ADCs by averaging four samples for one input voltage, while the rotating&averaging with redundancy has better static linearity improvement but less SNR improvement than the rotating&averaging without redundancy technique. The application of these two methods to 14-bit SAR ADC is demonstrated by Monte-Carlo runs, results show that with a mismatch error typical of modern technology, the proposed rotating&averaging with redundancy scheme can improve the root-mean-square of integral nonlinearity from 2.08 to 0.57 LSB, and the SFDR is more than 15 dB better. On the other hand, the averaged SNR of 7.7 dB is improved by using the proposed rotating&averaging without redundancy technique for a 14-bit SAR ADC. Furthermore, the schemes proposed require only small additional circuit on a typical SAR ADC configuration, which are more feasible to implement high-resolution SAR ADC compared with the traditional calibration schemes.

Integrated magnetic Hall effect sensors have been widely used in people's lives over the past decades. They are still gaining enormous attention from researchers to establish novel applications, especially in biochemistry and biomedical healthcare.

This paper presents a fast transient LDO with high power supply rejection ratio (PSRR) over 100-kHz based on adaptive biasing, dynamic biasing technique and a current mode feed-forward amplifier (CMFFA). The dynamic biasing improves the load transient response and the adaptive biasing benefits the loop stability. The CMFFA introduces a left-half-plane zero to compensate for the non-dominant pole without large current consumption. Moreover, a impedance adaptive circuit is also used in this design: it ensures the DC gain and pushes a nondominant pole to high frequency. Through these methods, the proposed LDO is stable over full load range, from 0mA to 150mA, it achieves fast transient response and high PSRR with a low quiescent current. The LDO is fabricated in a 0.6-μm CMOS technology. The output voltage can be regulated from 1.8V to 3.3V and the load capacitance is 1 μF. For a 150mA load step and a 3.3V output voltage, the maximum undershoot voltage is 38.6mV. At maximum load condition, a 41dB PSRR is achieved at 100-kHz and the loop gain bandwidth product is 1.9MHz. The DC gain is around 70dB over the full load range. The measured load regulation and line regulation are 0.06mV/mA and 1mV/V, respectively. The LDO has a minimum quiescent current of 9.6μA without load. Finally, the proposed LDO achieves a FOM1 of 16.47ps and a FOM2 of 123.52μV.

This article presents a fast-transient radiation-hardened low-dropout (LDO) voltage regulator integrated in a standard 0.6-μm BiCMOS technology for space and other harsh radiation environment applications. The fabricated LDO consumes 150- μA quiescent current at 6-A maximum output current. An LDO voltage of 300 mV which corresponds to an ultralow R _DS(ON) resistance of 500 mΩ is realized by accurate modeling. A separate fast-transient response circuit under narrow-bandwidth condition is proposed to improve the output voltage transient speed. It operates from an input voltage range of 2.8-5.5 V and provides an output voltage of 2.5 V, with output voltage accuracy of ±2%. The proposed LDO achieves a successful line regulation of 1 mV/V, and a load regulation of 2.16 mV/A. Effective radiation-hardened layout techniques are applied to realize high area-efficient LDO chip, whose total area including pads is 5.35 mm ² , which represents only about one-third area of similar radiation-hardened products. Furthermore, a special set of total ionizing dose (TID) experiments and single-event latch-up (SEL) experiments were performed. The measurement results show that the LDO can tolerate up to a TID of 150 krad (Si) and SEL immunity at a linear energy transfer (LET) of 99.8 MeV/(mg/cm ² ) with proposed layout design.