A new read scheme is proposed to suppress read disturbance in unselected strings of three-dimensional (3D) vertical channel flash memories. This new scheme decreases the channel potential difference between select word-line (WL) and adjacent WL by more than 20% and the read disturb due to hot carrier injection in adjacent WL of selected WL is suppressed effectively by about 95%. Meanwhile, boosted channel potential during read operation has been preserved to improve soft programming read disturbance by more than 85% in non-adjacent unselected memory cells, owing to the reduced electric field across tunnel oxide. Compared with the conventional scheme, the proposed scheme leads to a significant improvement in read disturbance characteristics with a shorter read period as well as a simplified waveform of read operation.

In this study, the wafer warpage resulting from common source line tungsten (CSL W) is investigated in 3D NAND flash memory. It is found that the warpage is related to the annealing conditions after CSL W deposition, and it reduces exponentially with increasing annealing temperature or linearly with increasing annealing time. This result shows that the effect of annealing temperature on warpage is greater than that of time. Consequently, spike annealing with a low thermal budget is proposed to achieve the desired reduction of warpage as long as the annealing temperature is adequate. This work provides an effective approach to solve the wafer warpage problem in 3D NAND flash memory manufacturing.

A new program scheme using an “erase-like” waveform for precharge operation is proposed for program disturbance optimization in 3-D vertical channel flash memories. With the proposed scheme, the effect of precharge operation, which is followed by program operation, on the initial unselected channel is enhanced by charging additional holes from p-type well. Consequently, boosting efficiency and boosting potential of unselected string are promoted, leading to a significant suppressed program disturbance, and the V _pass window can be enlarged notably as well. Meanwhile, the timing requirement of the proposed scheme is evaluated. The advantage of the erase assisted precharge scheme has been demonstrated by TCAD simulation and measurement in mini-array test-key device.

The disturbance mechanism of dummy cell during memory cell cycling has been investigated in 3D NAND flash. Edge dummy cell (DMY) threshold voltage increasing was observed during cell program and erase cycling, which leads to a reduced string current and read failure. According to experiment and TCAD analysis, two mechanisms were identified to contribute to the dummy disturbance: one is the tunneling of electrons from the adjacent gate to the trapping layer during cell erase condition, which was also observed in 2D NAND; the other one is the lateral charge spreading from the trapping layer of edge cell to DMY, which is a new observation for the junction-less 3D NAND with continuous nitride trapping layer. Furthermore, an optimal DMY bias scheme under erase operation is demonstrated to suppress the disturbance.

Erase cycling induced Vt shift of top select gate transistor (TSG) and its physical mechanism are studied in 3D NAND flash memory. It is found that the distribution of TSG Vt shifts higher during memory cells erase cycling. Furthermore, the TSG Vt shift can recover after the removal of cycling stress. A physical model of trap generation induced by hot holes is proposed for above observations. It is considered that hot holes generated by high channel potential gradient during erase can break the $\equiv $ Si–H bonds at the poly-Si grain boundary and the poly-Si/SiO 2 interface, causing TSG Vt tail shift and parallel shift, respectively. And the degradation can recover due to re-passivation of $\equiv $ Si–H bonds after stress removal. A TSG bias optimization scheme is demonstrated to reduce the hot holes generation and suppress the TSG abnormal Vt shift during cell erase cycling.