HfO 2-based thin films have raised considerable interest in ferroelectric memory devices due to their thickness scalability and process compatibility with CMOS.

As the 3D NAND technology developing toward more and more stack layers, it is essential to shrink the gate length (Lg) and inter-gate space (Ls). However, one of key concerns of scaling Lg/Ls 3D NAND flash is post-cycling data retention characteristics. The impact of cycling induced intercell trapped charge on two primary charge loss mechanisms (vertical and lateral charge loss) was studied in this work. According to experimental analysis and TCAD simulation, it is found that, in vertically scaled 3D NAND, the vertical charge loss is deteriorated not only by the cycling induced tunnel oxide degradation (introducing interface/oxide traps), but also by the cycling induced intercell trapped charge (enhancing word-lines edge electric field), on account of the enhanced Poole-Frenkel effect and tunneling effect. On the other hand, the cycling induced intercell trapped charge can also suppress lateral charge migration. Therefore, the vertical charge loss, rather than the lateral charge migration, still can be the dominant factor for post-cycling retention characteristics in scaling Lg/Ls 3D NAND flash memory.

3D NAND Flash with high storage capacity is in great demand for several technologies, which requires high performance and good reliability at the same time. Therefore, it is proposed to adjust the tunnel layer by changing the first SiO ₂ (O1) layer thickness near poly Si channel in the tunnel layer based on SiO ₂ /SiO _x N _y /SiO ₂ structure. The optimal thickness of O1 layer is found. Under the optimal condition, program speed increased by 19% compared with no O1 layer deposition, though erase speed is slightly decreased by about 7%, the initial threshold voltage shift is improved greatly. Experimental results demonstrate that there are complex mechanisms affected by the dielectric constant, band barrier and equivalent oxide thickness. The optimization of O1 layer is useful towards an understanding of program/erase speed and retention characteristics.

A new read scheme is proposed to suppress read disturbance in unselected strings of three-dimensional (3D) vertical channel flash memories. This new scheme decreases the channel potential difference between select word-line (WL) and adjacent WL by more than 20% and the read disturb due to hot carrier injection in adjacent WL of selected WL is suppressed effectively by about 95%. Meanwhile, boosted channel potential during read operation has been preserved to improve soft programming read disturbance by more than 85% in non-adjacent unselected memory cells, owing to the reduced electric field across tunnel oxide. Compared with the conventional scheme, the proposed scheme leads to a significant improvement in read disturbance characteristics with a shorter read period as well as a simplified waveform of read operation.

The impact of linear correlation between lognormal distribution grain size mean and sigma along the polysilicon channel on threshold voltage (Vth) variability has been investigated in three dimensional (3D) NAND flash. The variety of grain size mean and sigma results in the unstable Vth variability. To obtain a stable Vth distribution with various grain size mean, the grain size mean dependent Vth variability sensitivity to the grain size sigma was used to optimize the linear correlation between grain size mean and sigma via TCAD simulation. The optimized linear correlation with stable Vth variability is obtained except for the “unbalance region” affected by the combination of grain boundaries and positions with these grain size mean and sigma values resulting in the slightly shrinking Vth variability. Our results strongly suggest that this approach could guide the direction of polysilicon crystallization optimization to obtain stable Vth distribution with the predicted linear correlation between grain size mean and sigma.