A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3 digitally controlled oscillator required to manipulate the state of qubits.

Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16- $\mu \text{m}$ and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device dc characteristics, the accuracy and validity of the compact models are demonstrated by comparing time- and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.

This letter presents an area-efficient and PVT-insensitive segmented duty-cycled resistor (SDR) intended for neural recording amplifiers. The feedback resistor of the capacitively-coupled low noise amplifier is realized with segmentation of the polysilicon resistor and supplementary switches in between. The proposed SDR suppresses impedance reduction due to switching of the resistor’s parasitic capacitance. It ensures higher than 1 TΩ resistance and a switching frequency above the signal bandwidth simultaneously, thus removing in-band switching artifacts and output DC drift. Fabricated in 0.18-μm CMOS, the prototype SDR achieves up to 1.18 TΩ with the smallest temperature variation of 6.5 % and chip-to-chip variation of 1.5 %, while only occupying an area of 0.001375 mm. Furthermore, it offers sufficiently low and stable cut-off frequencies for both action and local field potential recordings.