This paper presents an ultra-low power acoustic sensing and object recognition microsystem for Internet of Things applications. The microsystem is targeted for unattended ground sensor nodes where long-term (decades) life time is desired without the need for battery replacement. The system incorporates an microelectromechanical systems microphone as a frontend sensor along with active circuitry to identify target objects. We introduce an algorithm-circuit cross optimization to realize a 12-nW stand-alone microsystem that integrates the analog frontend with the digital backend signal classifier. The frequency-domain analysis of target audio signals reveals that the system can operate with a relatively low bandwidth (3 dB) which significantly relaxes power constraints on both analog frontend and digital backend circuits. To further relax the current requirement of the preceding amplifier, we propose an 8-bit SAR-analog-to-digital converter that is designed to have a highly reduced sampling capacitance (95% reliability and consumes only 12 nW with continuous monitoring.

Miniaturized and wireless near-infrared (NIR)-based neural recorders with optical powering and data telemetry have been introduced as a promising approach for safe long-term monitoring with the smallest physical dimension among state-of-the-art standalone recorders. However, the main challenge for the NIR-based neural recording integrated circuits (ICs) is to maintain robust operation in the presence of light-induced parasitic short-circuit current from junction diodes. This is especially true when the signal currents are kept small to reduce power consumption. In this work, we present a light-tolerant and low-power neural recording IC for motor prediction that can fully function in up to 300 $\mu \text{W}$ /mm ² of light exposure. It achieves the best-in-class power consumption of 0.57 $\mu \text{W}$ at 38 °C with a 4.1 noise efficiency factor (NEF) pseudo-resistor-less amplifier, an on- chip neural feature extractor, and individual mote-level gain control. Applying the 20-channel pre-recorded neural signals of a monkey, the IC predicts finger position and velocity with a correlation coefficient up to 0.870 and 0.569, respectively, with individual mote-level gain control enabled. In addition, wireless measurement is demonstrated through optical power and data telemetry using a custom photovoltaic (PV)/light-emitting diode (LED) GaAs chip wire bonded to the proposed IC.

This article presents a low jitter, low power, low reference spur LC oscillator-based reference oversampling digital phase locked loop (OSPLL). The proposed reference oversampling architecture simultaneously offers a low in-band phase noise, a wide-bandwidth, and a low spur. In addition, this article proposes an LC digitally controlled oscillator (DCO) for the proposed OSPLL to achieve a fast frequency update and fine frequency resolution, while its varactor switching timing is set optimally for low jitter using the proposed DCO tuning pulse timing control scheme. The proposed OSPLL was fabricated in a 28-nm CMOS process. The integrated rms jitter of the PLL was measured at 67.1 fs for an output frequency of 4 GHz. The in-band phase noise of the PLL was −129.2 and −132.5 dBc/Hz at 1- and 5-MHz offset frequencies. The measured reference spur of the PLL was −78.1 dBc. Total PLL power consumption was 5.2 mW, resulting in −256.3-dB PLL jitter-power FoM, while occupying 0.17-mm ² area.

This letter proposes a discrete-time low-noise amplifier (LNA) achieving a 0.45 noise efficiency factor (NEF) and 0.2 power efficiency factor (PEF), the lowest reported values to date. We demonstrate a switched-capacitor (SC)-based series–parallel amplifier (SPA) used as a noise-efficient LNA, relaxing the noise requirements of the following chain and reducing the power consumption of the analog front-end. A successive-approximation amplifier (SAA) serves as a second variable-gain stage. The proposed LNA achieves 1.2- $\mu \text{V}_{\mathrm{ RMS}}$ input-referred noise by oversampling the input signal while consuming 680 nW, including all the contributions from the clock-distribution network and gate drivers. The CMRR and PSRR are 97.1 dB and 78.6 dB, respectively, and the THD is −71 dB at 20-mV ${_{PP}}$ input.

There has been a long-standing interest in controlling and instrumenting the human body. Whether to restore lost function with neural prosthetics, monitor blood glucose levels, or augment human capabilities, there are countless opportunities for sensors inside ( e.g., ingestible, injectable, and implantable) and outside ( e.g., wearable) the body. However, many challenges exist when instrumenting the body. First, many use cases ( e.g., implanted sensors) require long-term recording to capture anomalous behavior—sometimes with limited accessibility—necessitating ultralow power consumption. Second, the power reduction challenge is further exacerbated by size constraints, which limit battery capacity or harvestable energy levels. Third, the signals of interest are often low bandwidth (kHz) and small in amplitude (µV to mV); thus, low-noise front ends are needed. Addressing these challenges has led to a large body of work on the design of highly power-efficient, low-noise amplifiers for biomedical integrated circuits.