This brief presents a fast and energy-efficient level shifter with wide conversion range. To achieve both energy-efficient and high-speed voltage level conversion, a novel architecture combined with multi-threshold CMOS technique is employed in the proposed circuit. A mixed-threshold current mirror circuit is proposed to solve the reduced swing issue in the prior arts. Moreover, auxiliary bias circuits are inserted to guarantee that the low-threshold pull down networks could be strongly cut off while in leaking state. As a result, the power consumption would be reduced to a great extent. Measurement results based on SMIC 55-nm MTCMOS process demonstrate that the proposed level shifter could provide robust voltage conversion from 0.12V to 1.2V. At the target voltage of 0.3V, the proposed level shifter shows a propagation delay of 17.86ns, a static power of 73.95pW, and an energy per transition of 26.59fJ for input frequency of 1MHz.

This brief presents a modified radix-4 Fast Fourier Transform (FFT) signal flow graph, whose input and output both are in natural order. Compared with the conventional radix-4 signal flow graph, it does not buffer the result of the last stage or execute the bit-reverse operation to generate the result, but generates the result directly in the last stage. Thus, the number of iteration is reduced by one. In order to realize the proposed memory-based FFT processor by using the modified radix-4 FFT signal flow graph, a conflict-free strategy and corresponding memory-addressing scheme is proposed. At last, the hardware implementation for the proposed FFT processor is proposed. Through the adoption of this method, FFT processor of arbitrary point conforming to the radix-4 algorithm can be implemented. Compared with the previous memory-based FFT processors, the proposed FFT processor has less processing time under the similar or lower resource consumption.

To get a better tradeoff between the transient performance and current efficiency of Digital Low-Dropout (DLDO) regulator, this paper proposes an all-digital Low-Dropout (LDO) regulator with adaptive clock technique. The sample clock is supplied by a proposed digital oscillator (DOSC) whose output frequency can be changed seamlessly. The frequency of sample clock and loop gain boost adaptively when the output voltage undershoot/overshoot is detected. Proposed DLDO integrates a ripple controller to eliminate steady-state supply ripple and reduce steady-state power. The proposed DLDO is simulated at Semiconductor Manufacturing International Corporation (SMIC) 55 nm with 5.03e-4 mm2 active area. The simulation results show that the operating voltage of proposed DLDO can be down to 0.5 V and the peak current efficiency is 99.99%. The measured voltage undershoot is 40 mV and transient response time is 500 ns with load step of 10 to 800 uA.

This paper presents a novel PMOS read-port 8T SRAM cell, in which the read circuit is constructed by two cascaded PMOS transistors, and hence the leakage power is significantly optimized compared to the conventional 8T cell. Meanwhile, it also exhibits high area efficiency due to an equalized quantity of NMOS and PMOS transistors per cell. Furthermore, the proposed cell has sufficient potential to enhance performance by employing a Half-Schmitt inverter. The measurements indicate that the proposed cell outmatches conventional 8T cell in terms of leakage suppression and area saving, thus making it a superior choice for ultra low power applications.

A low-power, configurable auto-gain control loop for a digital hearing aid system on a chip (SoC) is presented. By adopting a mixed-signal feedback control structure and peak detection and judgment, it can work in automatic gain or variable gain control modes through a digital signal processing unit. A noise-reduction and dynamic range (DR) improvement technique is also used to ensure the DR of the circuit in a low-voltage supply. The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process. The measurement results show that in a 1 V power supply, 1.6 kHz input frequency and 200 mVp—p, the SFDR is 74.3 dB, the THD is 66.1 dB, and the total power is 89 μW, meeting the application requirements of hearing aid SoCs.