This work presents a 1-8b reconfigurable digital SRAM compute-in-memory (CIM) macro, which significantly improves array utilization and energy efficiency under different input and weight configurations compared to previous works. To ensure the array utilization under different configurations, a row-based bitwise-summation-first digital CIM architecture is proposed. In addition, to realize flexible switching between signed and unsigned operations, a complete 2’s complement encoding method is adopted, which makes the computation of the sign bits consistent with that of the magnitude bits when performing signed operations, thus ensuring that each row of the CIM array can store the sign of the weight. Due to the support of reconfigurable bit width, the proposed CIM macro can be widely used in various neural networks for optimal efficiency. In order to better apply the CIM macro to binarized neural networks, a configurable bitwise multiplier is presented, which supports both AND and XNOR operations. Moreover, since the power consumption of the adder tree occupies a major part of the digital CIM macro, a 4-2 compressor based adder tree is presented to further improve the energy efficiency. Measurement results based on 55nm CMOS process show that the proposed CIM macro achieves an energy efficiency of up to 2238TOPS/W at 1b/1b and 44.82TOPS/W at 4b/4b MAC operations.

This brief presents a fast and energy-efficient level shifter with wide conversion range. To achieve both energy-efficient and high-speed voltage level conversion, a novel architecture combined with multi-threshold CMOS technique is employed in the proposed circuit. A mixed-threshold current mirror circuit is proposed to solve the reduced swing issue in the prior arts. Moreover, auxiliary bias circuits are inserted to guarantee that the low-threshold pull down networks could be strongly cut off while in leaking state. As a result, the power consumption would be reduced to a great extent. Measurement results based on SMIC 55-nm MTCMOS process demonstrate that the proposed level shifter could provide robust voltage conversion from 0.12V to 1.2V. At the target voltage of 0.3V, the proposed level shifter shows a propagation delay of 17.86ns, a static power of 73.95pW, and an energy per transition of 26.59fJ for input frequency of 1MHz.

As basic components, optimizing power consumption of flip-flops (FFs) can significantly reduce the power of digital systems. In this article, an energy-efficient retentive true-single-phase-clocked (TSPC) FF is proposed. With the employment of input-aware precharge scheme, the proposed TSPC FF precharges only when necessary. In addition, floating node analysis and transistor level optimization are employed to further ensure the high energy efficiency of the FF without significantly increasing the area. Postlayout simulations based on SMIC 55-nm CMOS technology show that at a supply voltage of 1.2 V, the power consumption of the proposed FF is 84.37% lower than that of conventional transmission-gate flip-flop (TGFF) at 10% data activity. The reduction rate is increased to 98.53% as the data activity goes down to 0%. When the supply voltage decreases to 0.6 V, the proposed FF consumes only 0.411 fJ/cycle at 10% data activity, which is 84.23% lower than TGFF. Measurement results of ten test chips demonstrate the great energy efficiency of the proposed FF. Furthermore, the CK-to-Q delay of the proposed FF is 26.18% lower than that of TGFF at a supply voltage of 1.2 V.

As essential building blocks of sequential digital circuits, optimizing the power consumption of flip-flops (FFs) can significantly reduce the total energy of digital systems. This paper proposes an ultra-low power 25-transistor (29-T with reset function) true single-phase clocked (TSPC) flip-flop by eliminating all redundant charges and discharges. Floating nodes are compensated by transistor-level optimization, which also enables a fully static and contention-free FF circuit design. The proposed FF is implemented in 55 nm CMOS technology. Post-layout simulation results demonstrate that at a supply voltage of 0.6 V and 10% data activity, the proposed circuit consumes only 0.153 fJ/cycle.

In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed CSLAs reduced power consumption by 68.4–72.2% with a slight delay increase for different bit widths. As the dual carry adder had much fewer transistors than the two regular full adders, the area of the proposed CSLAs was reduced by 45.8–51.1%. The area-power-delay product of the proposed CSLA improved 5.1×–6.73× compared with the regular CSLA.

In this brief, an accurate low-power power-on-reset circuit is proposed. In order to get an accurate trip-voltage with little overhead, a low-power architecture based on current reference and current comparator is proposed. The reference current in the proposed power-on-reset circuit is mainly provided by the sub-threshold current of several native NMOS transistors, and a stable hysteresis window can be obtained by adjusting the number of enabled native NMOS transistors. Measurement results based on 55nm CMOS process show that the proposed power-on-reset circuit consumes only 32nW at the supply voltage of 0.5V. The measured power-on-reset trip-voltage is 0.45V with a temperature coefficient of $227~\mu \text{V}/^{\circ }\text{C}$ . Since the proposed power-on reset circuit consists of only 10 transistors, the area of the proposed power-on-reset circuit is as low as $67.5~\mu \text{m}^{2}$ .