9 February 2022 in Scientific Reports
Ferroelectrics offer a promising material platform to realize energy-efficient non-volatile memory technology with the FeFET-based implementations being one of the most area-efficient ferroelectric memory architectures. However, the FeFET operation entails a fundamental trade-off between the read and the program operations. To overcome this trade-off, we propose in this work, a novel device concept, Mott-FeFET, that aims to replace the Silicon channel of the FeFET with VO2- a material that exhibits an electrically driven insulator–metal phase transition. The Mott-FeFET design, which demonstrates a (ferroelectric) polarization-dependent threshold voltage, enables the read current distinguishability (i.e., the ratio of current sensed when the Mott-FeFET is in state 1 and 0, respectively) to be independent of the program voltage. This enables the device to be programmed at low voltages without affecting the ability to sense/read the state of the device. Our work provides a pathway to realize low-voltage and energy-efficient non-volatile memory solutions.
25 May 2023 in IEEE Transactions on Instrumentation and Measurement
This paper presents the design of an optimized hardware-based neural network (NN) called a Shift-Accumulate Binarized Neural Network (SABiNN). SABiNN is employed in detecting respiratory-related diseases such as sleep apnea (SA) among adults. Initially, a 3-hidden layer-based NN model was trained, validated, and tested with open-source apnea PSG datasets collected from the PhysioNET databank. Single lead ECG and pulse oximeter data were collected, pre-processed, and digitized for network training. The NN was later transformed into SABiNN, demonstrating model accuracy of 81.5% (CI: ± 3.5) with an energy efficiency of 5mJ on reprogrammable hardware. The precision rate of the model was further increased by re-designing the XNOR gate of the multiply-accumulate (MAC) operation with NAND gate-based XNOR. This re-design process significantly improved the overall model’s classification and precision. Further expansion of SABiNN was carried out to achieve a higher accuracy rate (over 88%) which was designed on the CMOS platform using a 130 nm open-source process design kit (PDK) developed by Google and Skywater. The proposed model on the CMOS platform utilized a chip area of 0.16 mm 2 and showcased an energy efficiency of 1pJ. A total of ~11k CMOS cells with two 16-bit input and one 1-bit output pins were utilized to realize the SABiNN on CMOS. The success of this design technique can be leveraged in developing a fully system-on-a-chip (SoC) integrated wearable system for sleep apnea detection.