Outsourcing of integrated circuit (IC) manufacturing and increasing sophistication of IC reverse engineering techniques have unleashed security threats such as intellectual property (IP) theft and insertion of hardware Trojans. In this article, we propose and implement a run-time reconfigurable camouflage logic technology based on ferroelectric field-effect transistor (FeFET). The technology simultaneously obfuscates design IP from zero-trust foundry and untrusted testing facility and thwarts reverse engineering and counterfeiting threat. We fabricate for the first time an eight FeFET-based circuit block and demonstrate in silico gate-level camouflaging by implementing three Boolean logic functions--NOR, NAND, and XNOR--in the same circuit topology using threshold voltage (V_T) programming of FeFET. We perform circuit simulations using empirically calibrated models to estimate power, latency, and area overhead. Compared with recent proposal of programmable camouflage logic using hot-carrier injection (HCI), FeFET offers an overhead reduction of 2x, 1.8x, and 2.8x in area, power, and delay, respectively.

Spatial linear transforms that process multiple parallel analog signals to simplify downstream signal processing find widespread use in multi-antenna communication systems, machine learning inference, data compression, audio and ultrasound applications, among many others. In the past, a wide range of mixed-signal as well as digital spatial transform circuits have been proposed—it is, however, a longstanding question whether analog or digital transforms are superior in terms of throughput, power, and area. In this paper, we focus on Hadamard transforms and perform a systematic comparison of state-of-the-art analog and digital circuits implementing spatial transforms in the same 65 nm CMOS technology. We analyze the trade-offs between throughput, power, and area, and we identify regimes in which mixed-signal or digital Hadamard transforms are preferable. Our comparison reveals that (i) there is no clear winner and (ii) analog-to-digital conversion is often dominating area and energy efficiency—and not the spatial transform.

With the rising threats of side-channel-attacks (SCA) and complexities of both on-chip and ambient environment, it is demanding to incorporate on-chip learnability into SCA anomaly detection. This will enable offline-trained models to adapt to the new power profiles of emerging SCA schemes, workloads, and varying environments. Existing SCA detection techniques often fall short in in-situ learning or pose excessive on-chip integration challenges due to resource and data demands. This paper presents a novel neuromorphic "compute-in-PUF" (CIPUF) architecture designed for SCA detection with on-chip learning capability and optimized area/energy/data overheads. We harness the PUF-based key generator as a hyperdimensional encoder, fostering few-shot learning capabilities. It showcases a state-of-the-art accuracy of 96% with offline training. While deployed on-chip, our architecture can adeptly re-calibrate its model at the introduction of unseen power profiles, and regain model accuracy by 45% with as few as 254 power trace samples during 0.45ms time frame. Meanwhile, compared with baseline design using separate PUF and learning modules, it achieves a area savings of 4.15X and energy savings of 12.8X. Nevertheless, it introduces a unique scalability advantages for both hardware key repository and learning accuracy for future technology.

Hyperdimensional computing (HDC) is a bio-inspired machine learning paradigm utilizing hyperdimensional spaces for data representation. HDC significantly improves the ability to learn from sparse data and enhances noise robustness, and also enables parallel computation. Despite these advantages, HDC's reliance on high dimensionality and operational simplicity can lead to increased hardware costs and potential security vulnerabilities. This paper introduces a novel HDC encoding strategy using variation-based analog entropy (VAE), aiming to reduce memory footprint, lower power/energy consumption, and enhance security with physically-unclonable entropy generation. The VAE cell, with high entropy robustness (30.23 -- 57.76 dB SNR) and a small footprint (10 transistors), allows HDC to achieve a 14.3× reduction in vector dimensions, a 4.4× decrease in unit entropy cell area, and a 2% increase in accuracy compared to binary/multi-bit HDC. These benefits lead to a 1.3 -- 4.4× area and a 327× leakage power reduction when compared to an SRAM baseline. We have designed custom low-power circuits that enable end-to-end analog entropy storage, distribution management, binding, permutation, and bundling. This analog implementation prevents data conversion during feature vector encoding, thereby significantly enhancing energy efficiency (48.5nJ per query). Furthermore, with hardware-secured basis vectors, data security is significantly improved, as evidenced by the markedly degraded visual distinguish-ability of retrieved image data and maximum of 11 dB lower PSNR.

Ventricular arrhythmias (VAs), particularly ventricular tachycardia and fibrillation, remain a leading cause of sudden cardiac death. Implantable cardioverter defibrillators (ICDs) can deliver life-saving shocks, but inappropriate shocks degrade patient outcomes and device efficiency. While deep learning has improved VA detection accuracy, it lacks uncertainty quantification (UQ), limiting clinical acceptability. This article introduces a Bayesian convolutional neural network (Bayes-CNN) accelerator, designed for real-time intracardiac electrogram classification within ICDs. It combines a fully digital 1-D convolution pipeline for feature extraction with a mixed-signal, compute-in-memory (CIM) Bayesian classifier. By embedding a 360-fJ/Sample Gaussian random number generator within the CIM tile, this 0.816-mm ${}^{\mathrm {\mathbf {2}}}$ design delivers 350-pW VA detection with UQ, enabling a selective prediction strategy that reduces inappropriate shocks without compromising reliability.