Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)¹promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory^2–5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware^6–17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM—a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST¹⁸and 85.7 percent on CIFAR-10¹⁹image classification, 84.7-percent accuracy on Google speech command recognition²⁰, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.

Neuromorphic computing shows promise for advancing computing efficiency and capabilities of AI applications using brain-inspired principles. However, the neuromorphic research field currently lacks standardized benchmarks, making it difficult to accurately measure technological advancements, compare performance with conventional methods, and identify promising future research directions. This article presents NeuroBench, a benchmark framework for neuromorphic algorithms and systems, which is collaboratively designed from an open community of researchers across industry and academia. NeuroBench introduces a common set of tools and systematic methodology for inclusive benchmark measurement, delivering an objective reference framework for quantifying neuromorphic approaches in both hardware-independent and hardware-dependent settings. For latest project updates, visit the project website (neurobench.ai).

Integrated recording of neural electrical potentials from the brain poses great challenges due to stringent dynamic range requirements to resolve small-signal amplitudes buried in noise amidst large artifact and stimulation transients, as well as stringent power and volume constraints to enable minimally invasive untethered operation. Here, we present a 16-channel neural recording system-on-chip with greater than 90-dB input dynamic range and less than 1-μVrms input-referred noise from dc to 500 Hz, at 0.8-μW power consumption, and 0.024-mm ² area per channel in a 65-nm CMOS process. Each recording channel features a hybrid analog-digital second-order oversampling analog-to-digital converter (ADC), with the biopotential signal coupling directly to the second integrator for high conversion gain and dynamic offset subtraction in the digital domain. This bypasses the need for high-pass filtering pre-amplification in neural recording systems, which often leads to signal distortion. The integrated ADC-direct neural recording offers record figureof-merit with a noise efficiency factor (NEF) of the combined front end and ADC of 1.81, and a corresponding power efficiency factor (PEF) of 2.6. Predictive digital autoranging of the binary quantizer further supports rapid transient recovery while maintaining fully dc-coupled operation. Hence, the neural ADC is capable of recording ≤ 0.01-Hz slow potentials as well as recovering from ≥ 200-mVpp transients within ≤ 1 ms that are important prerequisites to effective electrocortical recording for brain activity mapping. In vivo recordings from marmoset primate frontal cortex demonstrate its unique capabilities in resolving ultra-slow local field potentials indicative of subject arousal state.

Not all computing problems are created equal. The inherent complexity of processing certain classes of problems using digital computers has inspired the exploration of alternate computing paradigms. Coupled oscillators exhibiting rich spatio-temporal dynamics have been proposed for solving hard optimization problems. However, the physical implementation of such systems has been constrained to small prototypes. Consequently, the computational properties of this paradigm remain inadequately explored. Here, we demonstrate an integrated circuit of thirty oscillators with highly reconfigurable coupling to compute optimal/near-optimal solutions to the archetypally hard Maximum Independent Set problem with over 90% accuracy. This platform uniquely enables us to characterize the dynamical and computational properties of this hardware approach. We show that the Maximum Independent Set is more challenging to compute in sparser graphs than in denser ones. Finally, using simulations we evaluate the scalability of the proposed approach. Our work marks an important step towards enabling application-specific analog computing platforms to solve computationally hard problems.

Outsourcing of integrated circuit (IC) manufacturing and increasing sophistication of IC reverse engineering techniques have unleashed security threats such as intellectual property (IP) theft and insertion of hardware Trojans. In this article, we propose and implement a run-time reconfigurable camouflage logic technology based on ferroelectric field-effect transistor (FeFET). The technology simultaneously obfuscates design IP from zero-trust foundry and untrusted testing facility and thwarts reverse engineering and counterfeiting threat. We fabricate for the first time an eight FeFET-based circuit block and demonstrate in silico gate-level camouflaging by implementing three Boolean logic functions--NOR, NAND, and XNOR--in the same circuit topology using threshold voltage (V_T) programming of FeFET. We perform circuit simulations using empirically calibrated models to estimate power, latency, and area overhead. Compared with recent proposal of programmable camouflage logic using hot-carrier injection (HCI), FeFET offers an overhead reduction of 2x, 1.8x, and 2.8x in area, power, and delay, respectively.