This article presents a low-power, high-resolution, high dynamic range (DR) current-mode direct-to-digital converter (CM-DDC) using a noise-shaping triple-slope quantizer. Both thermal and quantization noises can be first-order shaped out of band, increasing the resolution effectively. High resolution can be realized without using a high sampling rate or high-order shaping architecture. A coarse-fine zoom style quantization is exploited, which reduces the conversion time and, thus, the power consumption of active circuit blocks with dynamic biasing. On the circuit level, a chopped current digital-to-analog converter (DAC) is proposed to reduce 1/ $f$ noise of the current DAC, enhancing the DR. The CM-DDC with light-emitting diode (LED) driver and digital control circuitry is implemented in a standard 55-nm CMOS process and characterized experimentally. The converter achieves a signal-to-noise and distortion-ratio (SNDR) of 94.7 dB and a cross-scale DR of 136.5 dB in 20-Hz bandwidth with 30- $\mu \text{W}$ power for photoplethysmography (PPG)/near-infrared spectroscopy (NIRS) applications. Thanks to the shortened conversion time, the converter’s sampling frequency and signal bandwidth can be adjusted to 200 Hz and 2 kHz, achieving 90.5- and 79.2-dB SNDR, respectively, which allows various current sensing applications. The proposed CM-DDC is also validated with on- body chest PPG measurement.

This paper presents a low-power chopper-stabilized capacitively-coupled frontend amplifier with auxiliary-path-based input impedance ( Z $_{\mathbf{in}}$ ) boosting. In order to achieve a high Z $_{\mathbf{in}}$ , a low noise and a small chip area, techniques on both system level and circuit level are implemented. On the system level, small capacitors ( C $_{\mathbf{in}}$ $=$ 0.5 pF, C $_{\mathbf{fb}}$ $=$ 25 fF) are used with a biased pseudo-resistor ( R $=$ 2.5 G $\Omega $ ) fed back to an amplifier internal node. As a result, a high achievable Z $_{\mathbf{in}}$ and low high-pass corner frequency are achieved. On the circuit level, an input capacitance shielded current feedback (CSCF) topology achieving effective 10 fF C $_{\mathbf{amp}}$ is proposed as the core of the capacitive feedback amplifier in order not to increase the input noise. Moreover, the design space of auxiliary-path-based boosting is explored to obtain the optimal value of buffer bandwidth and auxiliary capacitor size to save power. The amplifier and its Z $_{\mathbf{in}}$ boosting circuit are implemented in a standard 55 nm CMOS process and characterized experimentally. Measurement results show that the proposed amplifier provides an input noise density of 50 nV/ $\surd$ Hz, and an integrated noise of 0.85 $\mu$ V $_{\mathbf{rms}}$ in 200 Hz band. The Z $_{\mathbf{in}}$ is boosted to 1.92 G $\Omega $ at DC and 1.02 G $\Omega $ at 50 Hz with only 1.0 $\mu$ A in each auxiliary path buffer. The amplifier also archives 77 dB CMRR and 76 dB PSRR while consuming 20.3 $\mu$ W in total.