This paper presents a circuit design and an implementation of a four-channel 12-bit digital-to-analog converter (DAC) with high-voltage operation and radiation-tolerant attribute using a specific CSMC H8312 0.5-μm Bi-CMOS technology to achieve the functionality across a wide-temperature range from -55 °C to 125 °C. In this paper, an R-2R resistor network is adopted in the DAC to provide necessary resistors matching which improves the DAC precision and linearity with both the global common centroid and local common centroid layout. Therefore, no additional, complicated digital calibration or laser-trimming are needed in this design. The experimental and measurement results show that the maximum frequency of the single-chip four-channel 12-bit R-2R ladder high-voltage radiation-tolerant DAC is 100 kHz, and the designed DAC achieves the maximum value of differential non-linearity of 0.18 LSB, and the maximum value of integral non-linearity of -0.53 LSB at 125 °C, which is close to the optimal DAC performance. The performance of the proposed DAC keeps constant over the whole temperature range from -55 °C to 125 °C. Furthermore, an enhanced radiation-hardened design has been demonstrated by utilizing a radiation chamber experimental setup. The fabricated radiation-tolerant DAC chipset occupies a die area of 7 mm × 7 mm in total including pads (core active area of 4 mm × 5 mm excluding pads) and consumes less than 525 mW, output voltage ranges from -10 to +10 V.

This paper presents an external capacitor-less NMOS low-dropout (LDO) voltage regulator integrated with a standard CSMC 0.6 μm BiCMOS technology. Over a -55 ∘C to +125 ∘C temperature range, the fabricated LDO provides a stable and considerable amount of 3 A output current over wide ranges of output capacitance COUT (from zero to hundreds of μF ) and effective-series-resistance (ESR) (from tens of milliohms to several ohms). A low dropout voltage of 200 mV has been realised by accurate modelling. Operating with an input voltage ranging from 2.2 V to 5.5 V provides a scalable output voltage from 0.8 V to 3.6 V. When the load current jumps from 100 mA to 3 A within 3 μs, the output voltage overshoot remains as low as 50 mV without output capacitance, COUT. The system bandwidth is about 2 MHz, and hardly changes with load altering to ensure system stability. To improve the load transient response and driving capacity of the NMOS power transistor, a buffer with high input impedance and low output impedance is applied between the transconductance amplifier and the NMOS power transistor. The total area of fabricated LDO voltage regulator chip including pads is 2.1 mm×2.2 mm.