Neuromorphic computing shows promise for advancing computing efficiency and capabilities of AI applications using brain-inspired principles. However, the neuromorphic research field currently lacks standardized benchmarks, making it difficult to accurately measure technological advancements, compare performance with conventional methods, and identify promising future research directions. This article presents NeuroBench, a benchmark framework for neuromorphic algorithms and systems, which is collaboratively designed from an open community of researchers across industry and academia. NeuroBench introduces a common set of tools and systematic methodology for inclusive benchmark measurement, delivering an objective reference framework for quantifying neuromorphic approaches in both hardware-independent and hardware-dependent settings. For latest project updates, visit the project website (neurobench.ai).
14 January 2021 in IEEE Internet of Things Journal
A single-input and single-output (SISO) frequencymodulated continuous wave (FMCW) radar architecture is proposed and in vivo demonstrated for remote two-dimensional (2-D) localization (range and angular information) and vital signs monitoring of multiple subjects. The radar sensor integrates two frequency scanning antennas which allow angular separation and enable determining a 2-D map (range vs. angle) of a room environment from which people can be distinguished from objects and clutter. After technical tests to validate the functionality of the proposed architecture and data processing algorithm, a practical setup was successfully demonstrated to locate human volunteers, at different absolute distances and orientations, and to retrieve their respiratory and heart rate information. Experimental results show that this radar sensor can monitor accurately the vital signs of multiple subjects within typical room settings, reporting maximum mean absolute errors of 0.747 breaths-perminute and 2.645 beats-per-minute respectively for respiration rate and heartbeat. Practical applications arise for Internet of Things (IoT), ambient assisted living, healthcare, geriatric and quarantine medicine, automotive, rescue and security purposes.
17 March 2021 in IEEE Transactions on Biomedical Engineering
Objective: Over the last two decades, radar-based contactless monitoring of vital signs (heartbeat and respiration rate) has raised increasing interest as an emerging and added value to health care. However, until now, the flaws caused by indoor multipath propagation formed a fundamental hurdle for the adoption of such technology in practical healthcare applications where reliability and robustness are crucial. Multipath reflections, originated from one person, combine with the direct signals and multipaths of other people and stationary objects, thus jeopardizing individual vital signs extraction and localization. This work focuses on tackling indoor multipath propagation. Methods: We describe a methodology, based on accurate models of the indoor multipaths and of the radar signals, that enables separating the undesired multipaths from desired signals of multiple individuals, removing a key obstacle to real-world contactless vital signs monitoring and localization. Results: We also demonstrated it by accurately measure individual heart rates, respiration rates, and absolute distances (range information) of paired volunteers in a challenging real-world office setting. Conclusion: The approach, validated using a frequency-modulated continuous wave (FMCW) radar, was shown to function in an indoor environment where radar signals are severely affected by multipath reflections. Significance: Practical applications arise for health care, assisted living, geriatric and quarantine medicine, rescue and security purposes.
20 October 2016 in IEEE Journal of Solid-State Circuits
A 6.4 MS/s 13 b ADC with a low-power background calibration for DAC mismatch and comparator offset errors is presented. Redundancy deals with DAC settling and facilitates calibration. A two-mode comparator and 0.3 fF capacitors reduce power and area. The background calibration can directly detect the sign of the dynamic comparator offset error and the DAC mismatch errors and correct both of them simultaneously in a stepwise feedback loop. The calibration achieves 20 dB spur reduction with little area and power overhead. The chip is implemented in 40 nm CMOS and consumes 46 μW from a 1 V supply, and achieves 64.1 dB SNDR and a FoM of 5.5 fJ/conversion-step at Nyquist.
17 August 2022 in IEEE Journal of Solid-State Circuits
This article presents a bioinspired, event-driven neuromorphic sensing system (NSS) capable of performing on-chip feature extraction and “send-on-delta” pulse-based transmission, targeting peripheral nerve neural recording applications. The proposed NSS employs event-based sampling which, by leveraging the sparse nature of electroneurogram (ENG) signals, achieves a data compression ratio of $> 125\times $ , while maintaining a low normalized rms error (NRMSE) of 4% after reconstruction. The proposed NSS consists of three sub-circuits. A clockless level-crossing (LC) analog-to-digital converter (ADC) with background offset calibration has been employed to reduce the data rate, while maintaining a high signal to quantization noise ratio (SQNR). A fully synthesized spiking neural network (SNN) extracts temporal features of compound action potential (CAP) signals and consumes only 13 $\mu \text{W}$ . An event-driven, pulse-based body channel communication (Pulse-BCC) with serialized address-event representation (AER) encoding schemes minimizes transmission energy and form factor. The prototype is fabricated in 40-nm CMOS occupying a 0.32-mm 2 active area and consumes in total 28.2 and 50 $\mu \text{W}$ power in feature extraction and full diagnosis mode, respectively. The presented NSS also extracts temporal features of CAP signals with 10- $\mu \text{s}$ precision.
24 February 2009 in IEEE Transactions on Circuits and Systems I: Regular Papers
This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization technique to improve the performance of a delta-sigma (¿¿) fractional-N PLL. The proposed CP circuit achieves good up/down current matching, while the proposed linearization method enables the PFD/CP system to operate at an improved linear region. The proposed techniques are demonstrated in the design of a 2.4-GHz ¿¿ fractional-N PLL. The experimental results show these techniques considerably improve the in-band phase noise and fractional spurs. In addition, the proposed gated-offset CP topology further lowers the reference spurs by more than 8 dB over the conventional fixed-offset approach. This chip is implemented in the TSMC 0.18-¿m CMOS process. The fully-integrated ¿¿ fractional-N PLL dissipates 22 mW from a 1.8-V supply voltage.