Agentic chip design combines large language models with electronic design automation (EDA) tools to plan, execute, and revise design operations. Its effectiveness depends on how an agent translates requirements into executable tasks, interprets diagnostic information, and coordinates changes across design stages. This survey examines these relationships across digital design, agent architectures, EDA algorithm and tool development, and evaluation, with additional coverage of analog, mixed-signal, and radio-frequency applications. We compare agentic chip-design methods through the design representations they modify, the feedback used to select revisions, and the procedures used to check correctness and implementation quality. The analysis shows that broader agent control over designs and EDA software expands optimization opportunities while increasing the need to manage dependencies and verify changes across the design flow. We also compare benchmarks and evaluation methods, focusing on functional correctness, implementation quality, and computational cost. These comparisons identify research directions in specification interpretation, failure diagnosis, repository-level integration, cross-stage optimization, and efficient tool use. By synthesizing these findings, this survey aims to guide the research community in developing and evaluating more reliable and efficient chip-design agents.

With the rapid advent of generative models, efficiently deploying these models on specialized hardware has become critical. Tensor Processing Units (TPUs) are designed to accelerate AI workloads, but their high power consumption necessitates innovations for improving efficiency. Compute-in-memory (CIM) has emerged as a promising paradigm with superior area and energy efficiency. In this work, we present a TPU architecture that integrates digital CIM to replace conventional digital systolic arrays in matrix multiply units (MXUs). We first establish a CIM-based TPU architecture model and simulator to evaluate the benefits of CIM for diverse generative model inference. Building upon the observed design insights, we further explore various CIM-based TPU architectural design choices. Up to 44.2% and 33.8% performance improvement for large language model and diffusion transformer inference, and 27.3x reduction in MXU energy consumption can be achieved with different design choices, compared to the baseline TPUv4i architecture.

Emerging multimodal LLMs (MLLMs) exhibit strong cross-modality perception and reasoning capabilities and hold great potential for various applications at edge. However, MLLMs typically consist of a compute-intensive modality encoder and a memory-bound LLM decoder, leading to distinct bottlenecks for hardware designs. In this work, we present a multi-core CPU solution with heterogeneous AI extensions, which are based on either the compute-centric systolic array or memory-centric digital compute-in-memory (CIM) co-processors. In addition, dynamic activation-aware weight pruning and bandwidth management are developed to enhance bandwidth efficiency and core utilization, improving overall performance. We implemented our solution using commercial 22nm technology. For representative MLLMs, our evaluations show EdgeMM can achieve 2.84x performance speedup compared to laptop 3060 GPU.