Alexandre Truppel

Alexandre Truppel

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Alexandre Truppel

Chair of Electronic Design Automation, Technical University of Munich, Munich, Germany

Research Focus & Metrics

Academic Career Length

7Years (2020-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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4 February 2020 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verified
Journal Article
Open access
ATAlexandre Truppel
Alexandre Truppel
TTTsun-Ming Tseng
Tsun-Ming Tseng
Davide BertozziDavide Bertozzi
Davide Bertozzi
JAJose Carlos Alves
Jose Carlos Alves
USUlf Schlichtmann
Ulf Schlichtmann
Optical Networks-on-Chip (ONoCs) are a promising solution for high-performance multi-core integration with better latency and bandwidth than traditional Electrical NoCs. Wavelength-routed ONoCs (WRONoCs) offer yet additional performance guarantees. However, WRONoC design presents new EDA challenges which have not yet been fully addressed. So far, most topology analysis is abstract, i.e. overlooks layout concerns, while for layout the tools available perform Place and Route (P&R) but no topology optimization. Thus, a need arises for a novel optimization method combining both aspects of WRONoC design. In this paper such a method, PSION+, is laid out. This new procedure uses a linear programming model to optimize a WRONoC physical layout template to optimality. This templatebased optimization scheme is a new idea in this area that seeks to minimize problem complexity while keeping design flexibility. A simple layout template format is introduced and explored. Finally, multiple model reduction techniques to reduce solver run-time are also presented and tested. When compared to the state-ofthe-art design procedure, results show a decrease in maximum optical insertion loss of 41%.

28 September 2022 in Journal of Lightwave Technology
Verified
Journal Article
Closed access
ATAlexandre Truppel
Alexandre Truppel
TTTsun-Ming Tseng
Tsun-Ming Tseng
USUlf Schlichtmann
Ulf Schlichtmann
Optical Networks-on-Chip (ONoCs) are becoming more and more appealing due to rising network requirements in integrated circuits. One important aspect in ONoC design is the amount of crosstalk generated by the network because crosstalk and Signal-to-Noise Ratio (SNR) are strong limiting factors to network scale and performance. Calculation of crosstalk is thus essential for effective ONoC design. Motivated by this fact, we developed a new general linear algebra based method to calculate the steady-state of any system obeying a simple set of rules. We prove that ONoCs follow these rules and show how this general method can be applied in the particular case of ONoCs to calculate accurate first-order and infinite-order crosstalk and SNR results for any ONoC network.

23 June 2024
Verified
Conference Paper
Open access
ZZZhidan Zheng
Zhidan Zheng
LCLiaoyuan Cheng
Liaoyuan Cheng
KAKanta Arisawa
Kanta Arisawa
QLQingyu Li
Qingyu Li
ATAlexandre Truppel
Alexandre Truppel
USUlf Schlichtmann
Ulf Schlichtmann
Wavelength-routed optical networks-on-chip (WRONoCs) are well-known for providing high-speed and collision-free communication in multi-core processors. Previous work was unable to simultaneously reduce the design complexity and total optical power consumption of WRONoC. Besides, in current designs, each microring resonator (MRR), which is the key component of WRONoC, is configured to demultiplex to one specific wavelength. This significantly increases the MRR usage and the insertion loss. In this work, we adapt different types of ONoC routers into the mesh-based template. To reduce MRR usage, we take advantage of an important feature of MRR, multi-resonance, so that a single MRR can demultiplex signals on multiple wavelengths. To this end, we propose an efficient design method that synthesizes mesh-based WRONoCs using multi-resonance MRRs and existing optical routers to reduce total power consumption. The experimental results show that our method outperforms state-of-the-art design methods in significantly reducing MRR usage and optical power.

25 June 2025 in Journal of Lightwave Technology
Verified
Journal Article
Open access
ATAlexandre Truppel
Alexandre Truppel
TTTsun-Ming Tseng
Tsun-Ming Tseng
USUlf Schlichtmann
Ulf Schlichtmann
Optical Networks-on-Chip (ONoCs) are gaining traction in integrated circuits due to increasing network demands. Wavelength-Routed ONoCs (WRONoCs), a specialised subtype, further enhance performance by reducing network latency. To achieve efficient communication, WRONoC designs aim to maximise bandwidth and minimise crosstalk – two competing objectives requiring careful balance. This work introduces an improved Pareto Simulated Annealing algorithm broadly applicable to multi-objective combinatorial problems. Key advancements include enhanced parallelism and using an adaptive temperature schedule to ensure consistency across all cost dimensions. We apply this algorithm to the optimisation of bandwidth and crosstalk in any WRONoC design, where it handles all objectives separately or together, with the combined optimisation yielding Pareto fronts for trade-off analysis. We also use a substitute for the $\max$ objective function that accelerates solution improvement and achieves better final results. Results demonstrate that our algorithm significantly outperforms state of the art methods in solution quality ($1.14\times$ higher bandwidth on average) and runtime ($11176\times$ lower on average) while scaling effectively to substantially larger problem sizes (up to $8\times$ more network nodes).