Prof. Davide Bertozzi

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Academic Career Length

19Years (2008-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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30 April 2014 in Design Automation for Embedded Systems

Journal Article

The fast evolving landscape of on-chip communication

Davide Bertozzi

Giorgos Dimitrakopoulos

José Flich

Sören Sonntag

25 July 2024 in IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Journal Article

An Ultra-Low Cost and Multicast-Enabled Asynchronous NoC for Neuromorphic Edge Computing

Zhe Su

Simone Ramini

Demetra Coffen Marcolin

Alessandro Veronesi

Milos Krstic

Steven M. Nowick

Biological brains are increasingly taken as a guide toward more efficient forms of computing. The latest frontier considers the use of spiking neural-network-based neuromorphic processors for near-sensor data processing, in order to fit the tight power and resource budgets of edge computing devices. However, a prevailing focus on brain-inspired computing and storage primitives in the design of neuromorphic systems is currently bringing a fundamental bottleneck to the forefront: chip-scale communications. While communication architectures (typically, a network-on-chip) are generally inspired by, or even borrowed from, general purpose computing, neuromorphic communications exhibit unique characteristics: they consist of the event-driven routing of small amounts of information to a large number of destinations within tight area and power budgets. This article aims at an inflection point in network-on-chip design for brain-inspired communications, revolving around the combination of cost-effective and robust asynchronous design, architecture specialization for short messaging and lightweight hardware support for tree-based multicast. When validated with functional spiking neural network traffic, the proposed NoC delivers energy savings ranging from 42% to 71% over a state-of-the-art NoC used in a real multi-core neuromorphic processor for edge computing applications.

5 November 2018

Conference Paper

4 February 2020 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Journal Article

PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs

Optical Networks-on-Chip (ONoCs) are a promising solution for high-performance multi-core integration with better latency and bandwidth than traditional Electrical NoCs. Wavelength-routed ONoCs (WRONoCs) offer yet additional performance guarantees. However, WRONoC design presents new EDA challenges which have not yet been fully addressed. So far, most topology analysis is abstract, i.e. overlooks layout concerns, while for layout the tools available perform Place and Route (P&R) but no topology optimization. Thus, a need arises for a novel optimization method combining both aspects of WRONoC design. In this paper such a method, PSION+, is laid out. This new procedure uses a linear programming model to optimize a WRONoC physical layout template to optimality. This templatebased optimization scheme is a new idea in this area that seeks to minimize problem complexity while keeping design flexibility. A simple layout template format is introduced and explored. Finally, multiple model reduction techniques to reduce solver run-time are also presented and tested. When compared to the state-ofthe-art design procedure, results show a decrease in maximum optical insertion loss of 41%.

24 November 2022 in IEEE Journal of Quantum Electronics

Journal Article

Reconfigurable Optical Wireless Switches for On-Chip Interconnection

Optical Wireless Networks on- Chip have been recently proposed as alternative paradigm to overcome the communication bottleneck in computing architectures based on electrical networks. In this paper, we propose the design of a $3\times 3$ switching matrix for optical wireless on- chip interconnection. The design exploits integrated optical phased arrays to guarantee the communication among three transmitters and three receivers. In this work, the effect of multipath propagation in the on- chip multi-layer structure is taken into account, and the impact of the cladding layer thickness is evaluated. The proposed device is intended to interconnect multiple nodes assuring reconfigurability and high bandwidth.

7 November 2016

Conference Paper

Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip

Andrea Peano

Luca Ramini

Marco Gavanelli

Maddalena Nonato

Davide Bertozzi

The recent interest in emerging interconnect technologies is bringing the issue of a proper EDA support for them to the forefront, so to tackle the design complexity. A relevant case study is provided by wavelength-routed optical NoCs (WRONoCs), which add communication performance guarantees to the typical latency, throughput and power benefits of an optical link, thus providing an appealing technology for the photonic integration of high-end embedded systems. Typically, only abstract WRONoC models are considered to figure out architecture-level performance, and logic connectivity patterns for the quantification of the required signal strength (i.e., static power). However, this design practice overlooks the needed refinement step, where key physical parameters are assigned such as wavelengths of the optical channels, and size of the optical filters. This step is unfortunately not decoupled from the architectural evaluation, since its main constraint (i.e., avoiding routing faults) turns out to be a key limiter for both the network scale and the achievable communication parallelism. By proposing a formal methodology to select WRONoC parameters while avoding the routing fault concern, this paper aims at maximizing the levels of connectivity and/or of bit parallelism that WRONoCs can achieve, while relating their upper bounds to the uncertainty of the manufacturing process

About Me

Davide Bertozzi is a Reader in Advanced Processing Technologies at University of Manchester (United Kingdom). He got his PhD at University of Bologna in 2003 and was Associate Professor at University of Ferrara till 2023. The mission of his research is to stay at the forefront of system innovation by leveraging the enabling properties of interconnection architectures and emerging technologies. His research has led to more than 200 publications. He has been visiting researcher at Stanford University and at several semiconductor industries (STMicroelectronics, NEC America Labs, NXP, Samsung). In 2018 he received the Wolfgang Mehr Award from IHP Microelectronics, a Leibniz Institute for innovative microelectronics in Germany. He got 5 best paper awards and 4 nominations. He currently contributes to the activities for neuroscience simulation acceleration within the flagship EBRAINS 2.0 project. The recent focus of his research is on unfolding the potential of asynchronous interconnect technology to address the communication bottleneck in neuromorphic systems (he is member of the UKRI-funded IKC on neuromorphic computing) and a key enabler for heterogeneous 2.5D integration (he is a member of the IKC on heterogeneous integration). Finally, he is deeply involved in EU-funded WIDERA initiatives for spreading excellence (TAICHIP, TWIN-RELEC, AIDA4Edge) through research on AI chip design, reliable electronics and hybrid SNN/ANN deep learning architectures, respectively.

Prof. Davide Bertozzi

Prof. Davide Bertozzi

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About Me