This work presents a structured, CAD-assisted design flow to realize broadband on-wafer calibration structures, validated in the prefabrication phase, and extract the intrinsic device response up to (sub)mm-waves. The strict requirements imposed by the design rule checks (DRCs) of 22 nm CMOS technology are incorporated during the design phase of the fixture by using a scripted connectable tile elements approach. The minimum dimension of a critical feature of the fixture is then identified using a newly defined metric based on the correspondence between the EM field distribution in the fixture versus a non-perturbed case of the same standard (STD) artifact. A simulation test bench environment, augmented with experimental data, is then used to add the uncertainties arising from three main error contributors: vector network analyzer (VNA) receiver noise, probe placement error, and calibration residual errors. Including these errors allows for the generation of pre-silicon numerical uncertainty bounds, which are benchmarked with experimental data using calibration quality metrics and device-level parameters. Measurement results ranging from 1 to 325 GHz are presented to demonstrate the validity of the proposed approach to establish the quality of on-wafer calibration approaches integrated in the back-end of line of Si-based technologies and to validate the compact model of CMOS devices up to (sub)mm-waves.

This paper presents the design and experimental characterization of two low-noise amplifiers (LNAs) operating at 5 GHz, implemented in commercial 16 nm and 7 nm FinFET CMOS technologies. Both circuits employ a cascode common-source architecture, but adopt different design approaches. The 7 nm implementation was designed to achieve simultaneous noise and input matching through source degeneration and gate inductive tuning. In contrast, the 16 nm implementation was primarily optimized for the minimum noise figure using an iterative electromagnetic-aware design methodology. The measured results highlight the practical trade-off between theoretical simultaneous noise and impedance matching and the degradation introduced by large integrated passive components in deeply scaled FinFET technologies. While the 7 nm design achieved improved input and output matching around the target frequency, the required inductive network introduced additional passive losses that degraded the measured noise figure. Conversely, the 16 nm implementation achieved a lower measured noise figure through a simplified matching network, at the expense of a reduced input-matching performance. The comparison provides practical design insights into the implementation of RF front-end circuits in advanced FinFET technologies and highlights the impact of passive component losses on the achievable noise performance.