Today, many electronic circuits are required to be able to work effectively, even in environments exposed to ionizing radiation. This work examines the effects of ionizing radiation on shift registers realized in a bulk 16 nm FinFET technology, focusing on Single-Event Upset (SEU). An SEU occurs when a charged particle ionizes a sensitive node in the circuit, causing a stored bit to flip from one logical state to its opposite. This study estimates the saturation cross-section for the 16 nm FinFET technology and compares it with results from a 28 nm planar CMOS technology. The experiments were conducted at the SIRAD facility of INFN Legnaro Laboratories (Italy). The device under test was irradiated with the ion sources ⁵⁸$Ni$ and ²⁸$Si$, both with different tilt angles, to assess the number of SEUs with different LET and range values. Additionally, the study evaluates the effectiveness of the radiation-hardened by design technique, specifically the Triple Modular Redundancy (TMR), which is a technique commonly employed in planar technologies. However, in this particular case study, TMR proved to be ineffective, and the reasons behind this limitation are analyzed along with potential improvements for future designs.

This paper presents the design of an energy harvesting interface for multiple piezoelectric elements. The latter is targeted to be integrated in an air spring to convert the mechanical energy in electrical one usable to power a wireless sensor node. Modelling of the energy harvesting electronic circuit has been performed to optimize the management of the multiple signals provided by the piezoelectric elements in function of a variable electrical load. An experimental activity has been conducted to validate the circuit design and the tests results demonstrate a good agreement with the numerical ones, confirming the effectiveness of the proposed interface.

Nowadays, automotive wire harnesses have become very complex systems as the number of electronic components and Electronic Control Units (ECUs) inside a vehicle have increased dramatically. To manage this complexity, and to support the automotive systems of tomorrow, new communication techniques need to be investigated. In this work, a direct modulated Power-Line Communication (PLC) method is proposed to drastically reduce the number of interconnections and give advantages in cost, complexity, and weight. Two transmitter topologies based on a Switching Capacitor approach are presented and implemented in a Test Chip fabricated in a 180 nm HV-CMOS SOI technology. The proposal is validated by communication tests connecting the designed chip and a discrete component-based demonstrator receiver through an unshielded twisted pair cable. Compared to commercially available solutions, the proposed approach can reach a data rate of 2 Mbps, making it able to implement high-speed event-driven networks, such as the Controller Area Network (CAN).

In this paper, a Supply Embedded Communication (SEC) transceiver for automotive networks is proposed. In an SEC approach, power supply and communication take place on the same differential bus and thus the number of required cables is drastically reduced, leading to space, raw material consumption, and cost advantages. The proposed transceiver is realized in 180nm SOI CMOS technology and is capable of implementing 2Mbps high-speed networks. In addition to proving nominal transient operation, some critical aspects for an automotive application are analyzed. Electromagnetic compatibility (EMC) is evaluated by conducting emission tests, and finally, the robustness to external disturbances is tested by direct power injection (DPI) tests.

This paper presents the design and experimental characterization of two low-noise amplifiers (LNAs) operating at 5 GHz, implemented in commercial 16 nm and 7 nm FinFET CMOS technologies. Both circuits employ a cascode common-source architecture, but adopt different design approaches. The 7 nm implementation was designed to achieve simultaneous noise and input matching through source degeneration and gate inductive tuning. In contrast, the 16 nm implementation was primarily optimized for the minimum noise figure using an iterative electromagnetic-aware design methodology. The measured results highlight the practical trade-off between theoretical simultaneous noise and impedance matching and the degradation introduced by large integrated passive components in deeply scaled FinFET technologies. While the 7 nm design achieved improved input and output matching around the target frequency, the required inductive network introduced additional passive losses that degraded the measured noise figure. Conversely, the 16 nm implementation achieved a lower measured noise figure through a simplified matching network, at the expense of a reduced input-matching performance. The comparison provides practical design insights into the implementation of RF front-end circuits in advanced FinFET technologies and highlights the impact of passive component losses on the achievable noise performance.