Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

Design and Fabrication of Flexible Nanoantenna-Based Sensor Using Graphene-Coated Carbon Cloth: Carbon nanomaterials have attracted significant consideration and concern due to the unique chemical and physical properties. Recently, nanodiamonds, graphene, and carbon nanotubes are served as electrodes, hydrogen storage elements, and composite materials. In this work, a 5GHz graphene nanoantenna that falls inside the very-small-aperture terminal (VSAT) C-band range has been fabricated. A graphene substrate with a thickness of h=0.5cm is formed which is then used for fabricating a graphene nanoantenna working at 5GHz. To design and simulate the antenna, Analysis System (ANSYS) electromagnetic desktop software was used. Using the designed graphene antenna, the parameters such as voltage standing wave ratio, three-dimensional radiation pattern, and directivity were obtained. After designing of the antenna using ANSYS software, it was physically fabricated. The graphene was used as a dielectric, copper sheet acted as a patch over as well as ground. Finally, the design was testedusing Vector Network Analyzer (Model: N9925A) and the transmission range was found as 5GHz.

This article presents a 1×6 linear phased antenna array implemented with metamaterial incorporated patch antennas for 5G base stations. The single element antenna was modelled on Rogers RT/duroid 5880 substrate in the dimensions of 7.8×7.8×0.254 mm³ with metamaterial incorporated partial ground plane and complementary metamaterial incorporated patch. This metamaterial incorporated antenna structure is resonating in 22.03–33.55 GHz at central frequency of 28 GHz with 40% impedance bandwidth with respect to the –10 dB return losses. With aim to design a radiating structure for 5G base stations and in order to enhance the gain, a six element phased array was developed using the abovementioned single element antenna with inter element spacing 7.8 mm between the adjacent antenna elements. In the analysis of this phased array, we observed acceptable diversity parameters (isolation, ECC, DG, CCL, and MEG) and presented beam steering capabilities by changing the phase difference between the adjacent ports. The proposed six element phased array antenna is capable to steer the beam to ±43.5° and capable to cover 5G NR n-257, n-258 and n-261 bands with significant gain and efficiency.