Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

We demonstrate optical control of surface plasmon enhanced resonant terahertz transmission in two-dimensional subwavelength metallic hole arrays fabricated on gallium arsenide based substrates. Optically pumping the arrays creates a conductive layer in the substrate, reducing the terahertz transmission amplitude of both the resonant mode and the direct transmission. Under low optical fluence, the terahertz transmission is more greatly affected by resonance damping than by propagation loss in the substrate. An ErAs:GaAs nanoisland superlattice substrate is shown to allow ultrafast control with a switching recovery time of $\sim 10\text{ps}$ .

Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, the Anti-Symmetric Product Coding (APC) and Odd Multiple Storage (OMS) modules are utilized to implement the reconfigurable FIR filter (RFIR–APC–OMS). Herein, the APC–OMS module is used to reduce the area of the RFIR architecture. The performance of the RFIR–APC–OMS is analyzed in terms of: area, power, delay, LUT, flip flop, slices, and frequency. RFIR–APC–OMS has reduced 3.44% of area compared to the existing RFIR architecture employing the Dynamic Reconfigurable Partial Product Generator (DRPPG) module.

The multimedia applications and mobile communication systems require an efficient reconfigurable finite impulse response (RFIR) filter designs for achieving low area, power, cost, and high speed of system operation. In this paper, an efficient RFIR filter is designed based on the Radix-2 algorithm and Look-up-table Carry Select Adder (Radix 2 – LCSLA). Generally, the RFIR filter is controlled by multiplier and adder, which improves the performances of the filter. Hence, this research work is mostly concentrated on the multiplier and adder design. Here, the radix-2 algorithm is used instead of normal multiplier for multiplication operation in the RFIR filter design. Additionally, CSLA and LCSLA approaches used in the Radix-2 structure for adding partial products. The LCSLA has achieved better performance compared to the normal CSLA approaches. In this paper, both the Radix-2 algorithm and LCSLA approach improved the performances of the proposed RFIR filter design. The proposed RFIR filter design was implemented in the Xilinx and Cadence RTL compiler by using the Verilog code. The RFIR-Radix 2-LCSLA filter design was verified in the Modelsim by utilizing the Verilog code. The experimental result showed that the RFIR-Radix 2-LCSLA methodology has improved the performance of ASIC and FPGA in the RFIR filter design up to 5–15% compared to the existing filter architecture: DA-RFIR and LC-CBA-RFIR methods.

The scalable classifier mining technique proposed in this article aims to improve the accuracy and scalability of heart disease prediction models. This method employs a wide range of methodologies, including data preparation, feature selection, ensemble learning, and distributed computing, among others, to handle complicated patterns in large datasets quickly. By merging decision trees, random forests, and XGBoost classifiers with the Apache Spark distributed computing platform, the proposed method outperforms both traditional machine learning techniques and cutting-edge deep learning algorithms. The proposed method achieved an accuracy of 93.5%, which is higher than any of the conventional machine learning methods and comparable to or better than the most cutting-edge deep learning methods. By encompassing all of the essential processes, such as preprocessing, feature selection, ensemble learning, model merging, and distributed computing, this technique assures that the model is accurate, efficient, and easy to comprehend. As a result, it is an especially well-suited approach for clinical applications. The proposed technique has effectively shown its potential to increase the accuracy and scalability of heart disease prediction models, resulting in high accuracy, scalability, and interpretability.