Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects—discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.

The paper proposes two architectures for a dynamically scalable network-on-chip (NoC) for dynamically reconfigurable intellectual properties (IPs) to save power. The first architecture is a run-time scalable column-based NoC, where the columns of the NoC are scaled up and down at run-time depending on the demands to connect reconfigurable IPs. The second architecture is an extension of the first, where both the rows and columns of the NoC are dynamically scaled up and down on demand. A robust control manager is developed to control the IP and sub-NoC reconfigurations by optimizing the reconfiguration costs. The proposed architectures have been implemented and tested in actual prototypes on a Virtex 6 FPGA mounted on the ML605 board. The results show that dynamically scalable architectures are capable of significant power reduction as compared to traditional static architectures for the same size of the NoC. It is anticipated that the scalable NoC can be very useful for sharing the FPGA resources among IPs at runtime.

This exploratory study investigates the ISO standards for quality management in perspective of software industry. The objective is to examine the applicability of ISO standards generic quality guidelines on software process, product and organization. The frameworks of ISO are studied and understood. Different comparisons are developed and refined to find out the correlation or contrast between ISO standards and SEI's CMMI, largely adopted SQM framework. The study would find answers to the research questions through intensive literature review. The study will enhance the reader's understanding about the ISO standards and would also elaborate the usefulness of ISO in SQM perspective. The paper is also a pedagogic contribution to software engineering education.

Nature being so nonlinear provides substantial reasoning to study the nonlinear dynamics inherited by the systems. Almost all of the systems that exist are nonlinear and analysis of such type of systems is necessary to understand a certain phenomenon. This paper presents a qualitative analysis of a coupled van der Pol's oscillator with the study of limit cycles. In order to get an approximate analytical solution of coupled van der Pol's (CVDP) oscillator system, a well-known perturbation technique, Method of Multiple Scales (MMS), is used. Stability and periodic construction of the van der Pol's system is examined by means of Floquet Multipliers and Shooting Method. Eigenvalues of Monodromy Matrix, a by-product of shooting method, are analysed to distinguish between hyperbolic and non-hyperbolic solutions of the system.

Integration of FPGAs in datacenters might have different motivations from acceleration to energy efficiency, but the goal of better performance tops all. FPGAs are being utilized in a variety of ways today, tightly coupled with heterogenous computing resources, and as a standalone network of homogenous resources. Open source software stacks, propriety tool chain, and programming languages with advanced methodologies are hitting hard on the programmability wall of the FPGAs. The deployment of FPGAs in datacenters will neither be sustainable nor economical, without realizing the multi-tenancy in multiple FPGAs. Inter-FPGA communication among multiple FPGAs remained relatively less addressed problem this area. In this proposed study, we made a theoretical case as a potential solution for this bottleneck problem to realize multi-tenant multi-FPGAs in datacenters. The proposed scheme poses a challenge as well as an opportunity for the scientific community to contribute.

We are going to design and simulate low power fractional-N phase-locked loop (FNPLL) frequency synthesizer for industrial application, which is based on VLSI. The design of FNPLL has been optimized using different VLSI techniques to acquire significant performance in terms of speed with relatively less power consumption. One of the major contributions in optimization is contributed by the loop filter as it limits the switching time between cycles. Sigma-delta modulator attenuates the noise generated by the loop filter. This paper presents the implementation details and simulation results of all the blocks of optimized design.