In this paper, a built-in self-test and in situ analog circuit optimization platform is proposed and characterized. By integrating a fully digital optimization engine and self-test circuits along with circuits-under-optimization (CUO), this platform can automatically find an operating point that makes a good balance among multiple competing characteristic goals. Therefore, the arbitrary linear time-invariant CUO can be optimized even when there are large process-voltage-temperature variations and aging effects of devices. This platform is analyzed to determine the required accuracy of its building blocks in terms of noise and linearity. The feasibility of this platform is proved by a case study utilizing a Tow-Thomas bandpass biquad.

This paper introduces a switched-capacitor dc combiner suitable for energy harvesting applications. Since the dc voltage is small, addition of the voltages from different sources can boost the final output voltage with self-startup capability. This approach is valid for any number of dc voltage sources. To prove the energy harvesting principle, three sources are selected. The design of the three-input dc combiner, with no closed-loop controller, is fabricated in 0.13-μm CMOS technology and the chip area is 1.5 × 1.5 mm ² . With integrated tunable thyristor-based differential oscillators, the chip can combine power from all three inputs. Manual frequency modulation is used to deliver the maximum power to the load. The system has proven to be functional even if one or two of the sources is/are weak or not available. Finally, for indoor conditions, the power from three different solar cells is combined where 70 μW is harvested with an open-circuit voltage of 1.4 V and the short-circuit current of 160 μA.

This paper introduces a new class of ring oscillator (RO)-based filters that address linearity and process variance limitation of existing RO-based filters. A highly-linear process-tolerant RO filter topology is achieved by imitating the widely known active-RC topology in the phase domain. We propose utilizing a set of frequency detectors (FDs) and phase detectors (PDs) to extract both the frequency and phase information of an inverter-based RO to synthesize active filters in a way similar to integrator-based active-RC filters, which are synthesized using a set of capacitors and resistors, respectively. A zero compensation technique is proposed to extend the achievable bandwidth of the proposed topology. Also, a delay-locked loop (DLL)-based tuning scheme is introduced to achieve resilience over PVT variations. A prototype 5th-order, 2endash 22 MHz continuous-time Butterworth filter is presented in 130 nm CMOS technology to demonstrate the proposed topology. The filter consumes 6.2endash 8.9 mA from a 1 V supply and achieves 26.2 dB in-band IIP3. The filter achieves bandwidth variation less than ±3.5% over a temperature range of -40 °C to 85 °C and supply voltage range of 0.9endash 1.2 V.

Testing is an important part of the design flow in the semiconductor industry. Unfortunately, it also consumes up to half of the production cost. On-silicon stimulus generators and response analyzers can be integrated with the Device-Under-Test (DUT) to reduce production costs with a minimum increment in power and area consumption. This practice is known as the Built-In Self-Test (BIST). This work presents a single-tone generator for BIST applications that is based on the Harmonic-Canceling (HC) technique. The main idea is to cancel or filter out the harmonics of a square-wave signal in order to obtain a highly pure sine wave. The design challenges of this technique are the precise implementation of irrational coefficients in silicon and the strong dependence of the output’s linearity on the coefficients’ precision. In order to reduce this dependence, this work introduces an irrational coefficient generator that is based on the recursive use of special matrices called skew-circulant matrices (SCMs). A complete study of the SCM-based HC synthesizer, its properties, and the proposed implementation in 180 nm CMOS technology are presented. The measured results show that the proposed HC synthesizer is able to filter out up to the 47th harmonic of a given square wave and to generate signals from $0.8$ to 100 MHz with a maximum Spurious-Free Dynamic Range (SFDR) of 66 dB.

In this paper, the N-phase current driven passive mixer clocked by 1/N duty-cycle clocks is analyzed. The analysis shows that the N-phase passive mixer holds the property of impedance transformation, where it can frequency-translate baseband lowpass impedances into RF frequency to synthesize high-Q bandpass filters. This property can be used to replace the off-chip SAW filter in wireless receivers. For the proof of concept, the system is implemented in 65nm CMOS technology. The simulation results are in a close agreement with the theoretical results.

In this paper an integrated SAW-less narrowband RF front-end for direct conversion wireless receivers is presented. The analysis of the feedback system shows a shift of the center frequency f_RX for the overall RF bandpass filter from its nominal value f_LO. The proposed architecture incorporates a notch filter at 2f_LO to insure that there is no shift in f_RX. The design has been implemented in 65nm CMOS process. It consumes 44mA from a single 1.2V supply. Simulation results show a rejection of more than 15dB in a bandwidth of +/-500MHz around 2GHz due to the additional feedback loop. The theoretical and simulation results are in close agreement.