This paper presents the design of a wireless sensor network (WSN) system for smart estimation of soil conditions. The WSN is formed by very low-power autonomous sensor nodes and employs Internet-of-Things and cloud service communication protocols to generate spatial distribution maps of soil parameters at two different levels below ground. An artificial neural network is used to analyze the measured data and estimate the levels of phosphorus (P) in the soil. This feature eliminates the need to perform time-consuming laboratory analysis to continuously monitor the value of this nutrient. Considering the changing rate of soil phenomena throughout a day, a dynamic power management (DPM) strategy is applied, allowing the system to establish an adaptive balance between its energy consumption and the accuracy of phosphorus estimation. The proposed precision agriculture structure allows the implementation of a flexible methodology that can be adapted to different type of crops and agricultural regions. Experimental results obtained in the lab and on the field corroborate the system’s performance and reliability.

The Internet-of-Things (IoT) paradigm is under constant development and is being enabled by the latest research work from both industrial and academic communities. Among the many contributions in such diverse areas as sensor manufacturing, network protocols, and wireless communications, energy harvesting techniques stand out as a key enabling technology for the realization of batteryless IoT end-node systems. In this paper, we give an overview of the recent developments in circuit design for ultra-low power management units (PMUs), focusing mainly in the architectures and techniques required for energy harvesting from multiple heterogeneous sources. The paper starts by discussing a general structure for IoT end-nodes and the main characteristics of PMUs for energy harvesting. Then, an overview is given of different published works for multisource power harvesting, observing their main advantages and disadvantages and comparing their performance. Finally, some open areas of research in multisource harvesting are observed and relevant conclusions are given.

Since operational transconductance amplifiers (OTAs) form the basic building blocks of many analog systems, the compensation of three-stage OTAs has attracted a lot of attention in the literature. Many different solutions to the stability problem of such OTAs have been proposed over the past 20 years, with each solution exhibiting different properties or targeting a different application. This work surveys a broad selection of previously reported architectures and proposes a novel classification scheme that exposes features common to seemingly different compensation architectures and serves as a guideline for which type of OTA is suitable for a given application. In addition, a novel figure of merit (FoM) is proposed to guide the designer in deciding which OTA architecture suits the tradeoffs specific to the application at hand. Theoretical discussions are further reinforced by transistor-level simulation results.

Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) design. The surrogate has three main components: a set of Gaussian process regression models of the technology’s parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs. The proposed surrogate is $69X$ to $470X$ faster at evaluation compared with circuit simulations.

Modern Internet-of-Things (IoT) devices rely on energy harvesting to extend their battery life and create maintenance-free applications. However, energy from ambient sources is intermittent and unpredictable, which compromises the reliability of any system. Harvesting from multiple sources allows the collection of higher amounts of power, producing robust operation even in the presence of ambient variations. This paper describes the design of a fully integrated system that combines the energy delivered by four inputs. The proposed architecture applies a smart harvesting strategy based on the available power from the transducers. The two inputs with the most power are automatically selected and combined, while maximum power tracking is performed. If the other two sources still show some usable power, a two-way energy storage scheme allows their use to sustain the circuit's operation. The system was fabricated in a 0.13-μm CMOS technology. Experimental results demonstrate a peak tracking efficiency of 96%. The power conversion efficiency has a maximum of 87.2% at 198 μW of output power and 72% at 981 μW.

With the aggressive scaling of transistor dimensions, intrinsic device gains are dropping but the need for high-gain amplifiers still exists, resulting in a great interest in multi-stage amplifiers. Most existing amplifier topologies rely on Miller capacitors which achieve stability at the expense of reduced speed. In this paper, a new state feedback compensation strategy with gain enhancement using partial positive feedback is proposed whereby a multistage amplifier can be made output-compensated, thereby requiring no Miller capacitance while being able to drive a wide range of load capacitances. After a thorough theoretical analysis, a topology prototype is fabricated in a standard 130 nm CMOS technology and is able to drive loads from 90 nF-50 nF (~555x) using three discrete modes. The amplifier's power and bandwidth are scalable depending on the expected capacitive load range, with a maximum power consumption of (185μW) from a 1V supply. Comparison with state-of-the-art amplifiers shows superior small-signal performance and competitive large-signal performance while driving a significantly larger range of capacitive loads.