Deploying deep convolutional neural networks on edge devices remains challenging due to limited on-chip memory capacity, strict power budgets, and the high energy cost of off-chip DRAM access. Standard architectures such as ResNet offer strong accuracy but require tens of millions of parameters, making them impractical for low-power embedded systems. This work presents a systematic, hardware-aware framework for designing compact CNN architectures inspired by the ResNet family. The proposed design integrates depthwise–separable convolutions, low-rank channel decomposition, and a zero-parameter identity shortcut that mitigates rank bottleneck degradation. Unlike prior lightweight CNNs that introduce entirely new topologies via neural architecture search, our approach builds a compact architecture by composing three well-understood operators—depthwise separable factorization, low-rank bottleneck insertion, and identity-shortcut augmentation—each acting on a complementary dimension of the parameter space. The resulting ResNet for Edge is trained entirely from scratch. Compared with ResNet-18, it reduces the parameter count by 8.33× and the computational cost by 42.3× while retaining 90.5% of the baseline’s Top-1 accuracy on ImageNet, outperforming classical compact CNNs under similar model sizes. On the NVIDIA Jetson Orin Nano, the model reaches up to 1415 FPS and consumes only 327.2 J to process the entire 50,000-image ImageNet validation set—achieving the best accuracy-per-energy efficiency among all eight compared models—demonstrating superior power efficiency for edge deployment. These findings show that structured architectural design combining depthwise separable convolutions with low-rank shortcuts provides a practical pathway for building compact models suited to real-time, energy-constrained edge-AI applications.

The implementation of artificial intelligence models on edge devices is increasingly popular, bringing many values in reducing latency, effectively utilizing bandwidth, improving data security, enhancing privacy and reducing costs for users. However, this work poses many challenges in terms of accuracy, processing speed, hardware resources and model size for devices constrained by limited hardware. Binary Neural Network (BNN) is proposed as a potential solution to reduce resource requirements by using only 1 bit for quantizing. In this study, BNN network is optimized by binary quantizing both weights and activation functions with XNOR-popcout multiplication to optimize BNN network. The results show that BNN network model is lighter in memory footprint when deployed on hardware with limited computational resources, less computational time than conventional BNN network which helps the model execute faster as the network architecture becomes less complex, with acceptable accuracy on two datasets MNIST and Fashion MNIST. The proposed BNN model resul can be deployed on edge devices for IoT applications.

With the rapid advancements of information processing systems, winner- take-all (WTA) circuits have emerged as essential components in a wide range of cognitive functions and decision-making applications. Neuromorphic computing systems, inspired by the biological brain, utilize WTA circuits as selective mechanisms that identify and retain the strongest signal while suppressing all others. In this study, we present an effective time-domain WTA circuit with optimized multiple-input NOT AND (NAND) gate and delay circuit for neuromorphic computing applications. The circuit is evaluated using sinusoidal current inputs with varying phase delays, which successfully demonstrating precise winner selection. When applied to neuromorphic image recognition task, the enhanced time-domain WTA achieves an improvement of 0.2% in precision while significantly reducing power consumption, yielding a low figure of merit (FoM) of 0.03 µW/MHz, compared to the previous study with FoM of 0.25 µW/MHz. The optimized WTA circuit is highly promising for large-scale neuromorphic applications.