Convolution Neural Networks (CNNs) are gaining ground in deep learning and Artificial Intelligence (AI) domains, and they can benefit from rapid prototyping in order to produce efficient and low-power hardware designs. The inference process of a Deep Neural Network (DNN) is considered a computationally intensive process that requires hardware accelerators to operate in real-world scenarios due to the low latency requirements of real-time applications. As a result, High-Level Synthesis (HLS) tools are gaining popularity since they provide attractive ways to reduce design time complexity directly in register transfer level (RTL). In this paper, we implement a MobileNetV2 model using a state-of-the-art HLS tool in order to conduct a design space exploration and to provide insights on complex hardware designs which are tailored for DNN inference. Our goal is to combine design methodologies with sparsification techniques to produce hardware accelerators that achieve comparable error metrics within the same order of magnitude with the corresponding state-of-the-art systems while also significantly reducing the inference latency and resource utilization. Toward this end, we apply sparse matrix techniques on a MobileNetV2 model for efficient data representation, and we evaluate our designs in two different weight pruning approaches. Experimental results are evaluated with respect to the CIFAR-10 data set using several different design methodologies in order to fully explore their effects on the performance of the model under examination.

Traditional approaches to analyzing electromigration (EM) in on-chip interconnects are largely driven by semi-empirical models. However, such methods are inexact for the typical multisegment lines that are found in modern integrated circuits. This paper overviews recent advances in analyzing EM in on-chip interconnect structures based on physics-based models that use partial differential equations, with appropriate boundary conditions, to capture the impact of electron-wind and back-stress forces within an interconnect, across multiple wire segments. Methods for both steady-state and transient analysis are presented, highlighting approaches that can solve these problems with a computation time that is linear in the number of wire segments in the interconnect.

As semiconductor technologies continue to scale aggressively, electromigration (EM) has become critical in modern VLSI design. Since traditional EM assessment methods fail to accurately capture the complex behavior of multi-segment interconnects, recent physics-based models have been developed to provide a more accurate representation of EM-induced stress evolution. However, numerical methods for these models result in large-scale systems, which are computationally expensive and impractical for complex interconnect structures. Model order reduction (MOR) has emerged as a key enabler for scalable EM analysis, with moment-matching (MM) techniques offering a favorable balance between efficiency and accuracy. However, conventional Krylov-based approaches often suffer from limited frequency resolution or high computational cost. Although the extended Krylov subspace (EKS) improves frequency coverage, its symmetric structure introduces significant overhead in large-scale scenarios. This work introduces a novel MOR technique based on the asymmetric extended Krylov subspace (AEKS), which improves upon the conventional EKS by incorporating a sparsity-aware and computationally efficient projection strategy. The proposed AEKS-based moment-matching framework dynamically adapts the Krylov subspace construction according to matrix sparsity, significantly reducing runtime without sacrificing accuracy. Experimental evaluation on IBM power grid benchmarks demonstrates the high accuracy of our method in both frequency-domain and transient EM simulations. The proposed approach delivers substantial runtime improvements of up to 15× over full-order simulations and 100× over COMSOL, while maintaining relative errors below 0.5%, even under time-varying current inputs.

Data centers are computing facilities that house networks of electronic racks containing data processing and storage equipment, which face significant thermal management challenges due to increasing power densities and dynamic workloads. As a result, efficient thermal simulation is essential for ensuring system reliability, reducing energy consumption, and preventing hotspots caused by computational workloads. In this paper, we introduce a novel thermal simulation framework that leverages the matrix exponential and the Asymmetric Extended Krylov Subspace (AEKS) method to efficiently model and simulate large-scale computing environments under diverse workloads. Experimental results across multiple data center configurations demonstrate that the proposed approach achieves significant computational speedups compared to conventional arithmetic solvers and Model Order Reduction (MOR) techniques, while maintaining high accuracy in thermal simulations.

The rapid growth of circuit complexity has rendered Model Order Reduction (MOR) a key enabler for the efficient simulation of large circuit models. MOR techniques based on moment-matching are well established due to their simplicity and computational performance in the reduction process. However, moment-matching methods based on the ordinary Krylov subspace are usually inadequate to accurately approximate the original circuit behavior, and at the same time do not produce reduced-order models as compact as needed. In this paper, we present a moment-matching method which utilizes the extended and the asymmetric extended Krylov subspace (EKS and AEKS), while it allows the parallel computation of the transfer function in order to deal with circuits that have many terminals. The proposed method can handle large-scale regular and singular circuits and generate accurate and efficient reduced-order models for circuit simulation. Experimental results on industrial IBM power grids demonstrate that the EKS method can achieve an error reduction up to 85.28% over a standard Krylov subspace method, while the AEKS method greatly reduces the runtime of EKS, introducing a negligible overhead in the reduction error.

As integrated circuit technologies are moving to smaller technology nodes, Electromigration (EM) has become one of the most challenging problems facing the EDA industry. While numerical approaches have been widely deployed since they can handle complicated interconnect structures, they tend to be much slower than analytical approaches. In this paper, we present a fast semi-analytical approach, based on the matrix exponential, for the solution of Korhonen's stress equation at discrete spatial points of interconnect trees, which enables the analytical calculation of EM stress at any time and point independently. The proposed approach is combined with the extended Krylov subspace method to accurately simulate large EM models and accelerate the calculation of the final solution. Experimental evaluation on OpenROAD benchmarks demonstrates that our method achieves 0.5% average relative error over the COMSOL industrial tool while being up to three orders of magnitude faster.