As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate input pins exhibit a significant Miller effect. Over recent years, the semiconductor industry has adopted current source models (CSMs) for accurate gate modeling. Industrial gate models, however, are precharacterized assuming capacitive loads, which poses significant challenges to the approximation of the highly resistive load interconnect with an effective capacitance (Ceff). In fact, most related works are either computationally expensive or unable to approximate the output slew. Furthermore, they require additional precharacterization and ignore the Miller effect. In this article, we present an iterative methodology for fast and accurate gate delay estimation. The proposed approach accurately computes the driver output waveform, using closed-form formulas to calculate a Ceff per waveform segment, while accounting for their interdependence. Thus, it allows for variable analysis resolution exploiting an accuracy/runtime tradeoff. In contrast to prior works, our approach is compatible with conventional CSMs and considers the impact of Miller capacitance. We evaluate our method on representative driver-load test circuits consisting of interconnects with arbitrary RC characteristics and ASU ASAP 7-nm standard cells. The proposed method achieves 1.3% and 2.5% delay and slew root-mean-square percentage error (RMSPE) against SPICE, respectively. In addition, it provides high efficiency, as it converges in 2.3 iterations on average.

Multiple Input Switching (MIS) effects commonly induce undesired glitch pulses at the output of CMOS gates, potentially leading to circuit malfunction and significant power consumption. Thus, accurate and efficient glitch modeling is crucial for the design of high-performance, low-power, and reliable ICs. In this work, we present a new gate-level approach for modeling glitch effects under MIS. Unlike previous studies, we leverage efficient Machine Learning (ML) techniques to accurately estimate the glitch shape characteristics, propagation delay, and power consumption. To this end, we evaluate various ML engines and explore different Artificial Neural Network (ANN) architectures. Moreover, we introduce a seamless workflow to integrate our ANNs into existing standard cell libraries, striking an optimal balance between model size and accuracy in gate-level glitch modeling. Experimental evaluation on gates implemented in 7 nm FinFET technology demonstrates that the proposed models achieve an average error of 2.19% against SPICE simulation while maintaining a minimal memory footprint.

Radiation-induced soft errors in Integrated Circuits (ICs) have always been a matter of great reliability concern. However, the ongoing shrinking of CMOS technology nodes, which results in high frequency, low power, and small area exacerbates the problem. Thus, accurate evaluation of the ICs’ vulnerability to such errors has become crucial, especially when a radiation-hardening process is developed. In this article, we present a gatelevel Soft Error Rate (SER) estimation framework based on an event-driven approach that models the generated Single Event Transients (SETs) as event pairs that propagate through the circuit. Dynamic Timing Analysis (DTA) is performed to estimate SET arrival times at Flip-Flop (FF) inputs and detect a soft error. Moreover, our approach approximates the glitch height and considers the noise immunity thresholds of gates to evaluate potential SET electrical masking. Additionally, our event-driven framework enables accurate propagation of Single Event Multiple Transients (SEMTs), which have become commonplace in combinational circuits. Experimental evaluation on ISCAS ’89 benchmarks indicates that the proposed event-driven height-aware approach exhibits 21.06% more accurate SER estimation on average, compared to conventional graph-based techniques, with respect to SPICE simulation. F1 scores further strengthen the previous result, demonstrating an average improvement of 11.86%. In terms of failures in time, experimental results show that the graph-based approach overestimates SER by an average of 8558 and up to 16485 errors compared to the proposed method. Finally, our approach is used to effectively identify the most sensitive gates that could potentially be hardened in a SER mitigation scenario.

As semiconductor technologies continue to scale aggressively, electromigration (EM) has become critical in modern VLSI design. Since traditional EM assessment methods fail to accurately capture the complex behavior of multi-segment interconnects, recent physics-based models have been developed to provide a more accurate representation of EM-induced stress evolution. However, numerical methods for these models result in large-scale systems, which are computationally expensive and impractical for complex interconnect structures. Model order reduction (MOR) has emerged as a key enabler for scalable EM analysis, with moment-matching (MM) techniques offering a favorable balance between efficiency and accuracy. However, conventional Krylov-based approaches often suffer from limited frequency resolution or high computational cost. Although the extended Krylov subspace (EKS) improves frequency coverage, its symmetric structure introduces significant overhead in large-scale scenarios. This work introduces a novel MOR technique based on the asymmetric extended Krylov subspace (AEKS), which improves upon the conventional EKS by incorporating a sparsity-aware and computationally efficient projection strategy. The proposed AEKS-based moment-matching framework dynamically adapts the Krylov subspace construction according to matrix sparsity, significantly reducing runtime without sacrificing accuracy. Experimental evaluation on IBM power grid benchmarks demonstrates the high accuracy of our method in both frequency-domain and transient EM simulations. The proposed approach delivers substantial runtime improvements of up to 15× over full-order simulations and 100× over COMSOL, while maintaining relative errors below 0.5%, even under time-varying current inputs.

With continuous technology scaling, accurate and efficient Multiple Input Switching (MIS) modeling is essential for designing high-performance, low-power, and reliable integrated circuits. MIS commonly induces speed-up or slow-down effects on gate timing and may even generate spurious glitches at the outputs, potentially impacting timing, power consumption, and overall circuit reliability. In this article, we propose a unified MIS modeling approach based on Machine Learning (ML), employing efficient and compact Artificial Neural Networks (ANNs) to estimate the timing and power characteristics of MIS-induced transitions and glitches. To achieve this, we evaluate various ML engines and explore different ANN hyperparameters and architectures. Moreover, we introduce an iterative workflow that seamlessly integrates our ANNs into standard cell libraries, striking an optimal balance between model accuracy and size. The proposed framework employs efficient techniques to reduce characterization effort, minimize library size, and improve model accuracy. Experimental evaluation on gates implemented in 7nm FinFET and 45nm bulk CMOS technologies indicates that our models exhibit a strong correlation with SPICE, achieving a mean R² score of 0.997 across all gates and process, voltage, and temperature corners while maintaining low memory demands. Thus, our approach can effectively improve gate-level timing, power, and reliability analysis and guide glitch reduction techniques.