Tao Su

Dr. Tao Su

School of Electronics and Information Technology, Sun Yat-sen University Guangzhou, Guangdong, China
orcid

Research Focus & Metrics

Academic Career Length

14Years (2013-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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5 December 2023 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verified
Journal Article
Closed access
SLSi-Huang Liu
Si-Huang Liu
CKChia-Yi Kuo
Chia-Yi Kuo
YMYan-Nan Mo
Yan-Nan Mo
Tao SuTao Su
Tao Su
The Number Theoretic Transform (NTT) is a widely adopted method for accelerating polynomial multiplication in lattice-based cryptosystems. Consequently, numerous hardware accelerators have been developed to enhance the speed of the NTT algorithm. Area-Time Product (ATP) and configurability are critical metrics for evaluating these accelerators. ATP measures efficiency, while configurability ensures adaptability to various algorithm parameters and hardware limitations. In this article, we propose an area-efficient, conflict-free, and configurable architecture for accelerating NTT/inverse NTT (INTT). The proposed architecture demonstrates adaptability to various parameter settings while maintaining a consistently low ATP, even under a high level of parallelism. Moreover, our architecture supports polynomials of different degrees after compilation, further enhancing its versatility. To minimize latency, we adopt the existing merged Constant-Geometry (CG) NTT and INTT algorithm to combine preprocessing and postprocessing and further eliminate the bit-reverse operation in the algorithm. Building upon this foundation, we propose low-complexity memory access patterns for polynomial coefficients and twiddle factors, which contribute to high area efficiency and configurability in our architecture. The implementation results on FPGA substantiate that the proposed architecture exhibits remarkable superiority over existing works in terms of configurability and area efficiency.

4 August 2020 in IEEE Transactions on Circuits and Systems for Video Technology
Verified
Journal Article
Closed access
YHYewen Huang
Yewen Huang
SLSicheng Lian
Sicheng Lian
HHHaifeng Hu
Haifeng Hu
DCDihu Chen
Dihu Chen
Tao SuTao Su
Tao Su
The past few years in the fields of Person Re-Identification (RE-ID) have seen attention mechanism receives enormous interest as it has superior performance in obtaining discriminative feature representations. However, a wide range of state-of-the-art RE-ID attention models only focus on one-dimensional attention design method, e.g. spatial attention and channels attention, hence the produced attention maps are neither detailed enough nor discriminative enough to capture complicated interactions of visual parts. Developing multi-scale attention mechanism for RE-ID, an under-studied approach, becomes a practicable method to overcome this deficiency. Toward this goal, we propose a Multiscale Omnibearing Attention Networks (MOAN) for RE-ID which is capable of utilizing the complex fusion information acquired from the multiscale attention mechanism with features being more representative. Specifically, MOAN takes full advantage of multi-sized convolution filters to obtain discriminative holistic and local feature maps, and adaptively conducts feature information augmentation by introducing an Omnibearing Attention (OA) module. Through the OA module, spatial attention and channel attention are integrated together in a unique way where they work in a complementary way. To sum up, MOAN not only inherits the merit of two kinds of attention mechanism but also performs well in extracting comprehensive feature information. Furthermore, taking into account the robustness of model performance, we formulate a Random Drop (RD) Function to facilitate training MOAN and further increase the diversity of training model for adaptation. Furthermore, to achieve end-to-end training, we utilize trainable parameters to take place of initial fixed parameters, and the model performance is experimentally promoted. Extensive experiments have been carried out on the four mainstream RE-ID datasets. As the result shows, our method with re-ranking achieves rank-1 accuracy of 92.29% on CUHK03-NP, 97.45% on Market-1501, 93.81% on DukeMTMC-reID and 81.53% on MSMT17-V2, outperforming the state-of-the-art methods and confirming the effectiveness of our method.

17 August 2022 in IEEE Transactions on Circuits and Systems for Video Technology
Verified
Journal Article
Closed access
SYShengrong Yang
Shengrong Yang
WLWeihong Liu
Weihong Liu
YYYangbin Yu
Yangbin Yu
HHHaifeng Hu
Haifeng Hu
DCDihu Chen
Dihu Chen
Tao SuTao Su
Tao Su
In this paper, we propose a Diverse Feature Learning Network with Attention Suppression and Part Level Background Suppression (DFLN) for person re-identification (ReID). DFLN includes two key components: attention suppression mechanism (ASM) and part level background suppression mechanism (PLBSM). Firstly, despite attention mechanism has made great progress in current state-of-the-art ReID methods, they can only pay attention to the most salient region but ignore other discriminative information limiting the diversity of networks, which is not optimal for ReID due to the models tend to match persons by diverse clues (e.g., legs, arms, body, logo of clothes). To tackle the limitation above, we propose the ASM to assist the network to make full use of the most salient features and capture the other sub-salient features, so as to attain diverse features to improve the network performance. Secondly, we adopt a novel PLBSM to develop the part-based method which is proved effective for enhancing the diversity of ReID network. The PLBSM consists of a part feature refined module and a background suppression loss function, and aims to attain pure part level feature by filtering background clutter. Our DFLN integrates the ASM and part-based method developed by PLBSM into an end-to-end network and is able to extract robust diversity feature representations leading to higher performance. Extensive experimental results demonstrate the effectiveness of each component and our method achieves state-of-the-art results on mainstream person re-identification datasets.

9 June 2023 in IEEE Transactions on Circuits and Systems for Video Technology
Verified
Journal Article
Closed access
WZWei Zhou
Wei Zhou
ZZZhijie Zheng
Zhijie Zheng
Tao SuTao Su
Tao Su
HHHaifeng Hu
Haifeng Hu
Multi-label image classification is a fundamental yet challenging task, which aims to predict the labels associated with a given image. Most of previous methods directly exploit the high-level features from the last layer of convolutional neural network for classification. However, these methods cannot obtain global features due to the limited size of convolutional kernels, and they fail to extract multi-scale features to effectively recognize small-scale objects in the images. Recent studies exploit the graph convolution network to model the label correlations for boosting the classification performance. Despite substantial progress, these methods rely on manually pre-defined graph structures. Besides, they ignore the associations between semantic labels and image regions, and do not fully explore the spatial context of images. To address above issues, we propose a novel Dual Attention Transformer (DATran) model, which adopts a dual-stream architecture that simultaneously learns spatial and channel correlations from multi-label images. Firstly, in order to solve the problem that current methods are difficult to recognize small-size objects, we develop a new multi-scale feature fusion (MSFF) module to generate multi-scale feature representation by jointly integrating both high-level semantics and low-level details. Secondly, we design a prior-enhanced spatial attention (PSA) module to learn the long-range correlation between objects from different spatial positions in images to enhance the model performance. Thirdly, we devise a prior-enhanced channel attention (PCA) module to capture the inter-dependencies between different channel maps, thus effectively improving the correlation between semantic categories. It is worth noting that PSA module and PCA module complement and promote each other to further augment the feature representations. Finally, the outputs of these two attention modules are fused to obtain the final features for classification. Performance evaluation experiments are conducted on MS-COCO 2014, PASCAL VOC 2007 and VG-500 datasets, demonstrating that DATran model achieves better performance than current state-of-the-art models.

17 October 2022 in IEEE Antennas and Wireless Propagation Letters
Verified
Journal Article
Closed access
ZLZe-Kai Luo
Ze-Kai Luo
Tao SuTao Su
Tao Su
Kai-Da XuKai-Da Xu
Kai-Da Xu
A new design for dual-wideband microstrip patch antenna is proposed in this paper. A dual-band characteristic is obtained with the help of four loaded shorting vias. To widen both lower and upper impedance bandwidth, parasitic annular sectors are employed to introduce two additional resonant modes. For further demonstration, a prototype is manufactured and tested. The measured results which are close to the simulated results indicate that the proposed antenna can achieve 10-dB impedance bandwidth of 10.4% from 2.37 GHz to 2.63 GHz with a maximum realized gain of 5.2 dBi and 14.3% from 5.52 GHz to 6.37 GHz with a maximum realized gain of 6 dBi. Along the whole operating band, the antenna radiates similar patterns which resemble those generated by a monopole antenna. With these advantages, this proposed work is suitable to be applied in the WLAN communications.

31 October 2022 in Electronics
Verified
Journal Article
Open access
PDF file
XYXin Yang
Xin Yang
Tao SuTao Su
Tao Su
The topic of transformers is rapidly emerging as one of the most important key primitives in neural networks. Unfortunately, most hardware designs for transformers are deficient, either hardly considering the configurability of the design or failing to realize the complete inference process of transformers. Specifically, few studies have paid attention to the compatibility of different computing paradigms. Thus, this paper presents EFA-Trans, a highly efficient and flexible hardware accelerator architecture for transformers. To reach high performance, we propose a configurable matrix computing array and leverage on-chip memories optimizations. In addition, with the design of nonlinear modules and fine-grained scheduling, our architecture can perform complete transformer inference. EFA-Trans is also compatible with dense and sparse patterns, which further expands its application scenarios. Moreover, a performance analytic model is abstracted to guide the determination of architecture parameter sets. Finally, our designs are developed by RTL and evaluated on Xilinx ZCU102. Experimental results demonstrate that EFA-Trans provides 23.74× and 7.58× improvement in energy efficiency compared with CPU and GPU, respectively. It also shows DSP efficiency is between 3.59× and 21.07× higher than others, outperforming existing advanced works.