This review addresses the intervehicular communication in Connected Vehicles (CV) by emphasizing V2V (vehicle-to-vehicle) and V2I (vehicle-to-infrastructure) communications in terms of evolution, current standards, state-of-the-art studies, embedded devices, simulation, trends, challenges, and relevant legislation. This review is based on studies conducted from 2009 to 2019, government reports about the sustainable deployment of these technologies and their adoption in the Brazilian automotive market. Moreover, WAVE (Wireless Access in Vehicular Environment) and DSRC (Dedicated Short-range Communication) standards, the performance analysis of communication parameters and intervehicular available at the market are also described. The current status of ITS (Intelligent Transportation System) development in Brazil was reviewed, as well as the research institutes and governmental actions focused on introducing the concept of connected vehicles into the society. The Brazilian outlook for technological adoption concerning CVs was also discussed. Moreover, challenges related to technical aspects, safety and environmental issues, and the standardization for vehicle communication are also described. Finally, this review highlights the challenges and proposals from available technologies devoted to the roads and vehicular infrastructure communication, their evolution and upcoming trends.

An analog synthesizer of orthogonal signals for digital CMOS technology and 3V supply voltage is presented. The adaptive architecture accomplishes the synthesis of mutually orthogonal signal, such as trigonometric and polynomial basis. Experimental results using 0.35µm AMS CMOS process are presented for generation of the cosine and Legendre basis.

An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mum AMS CMOS process and 1.5 V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.

Time-to-digital converter (TDC) has been the main technique used in all-digital phase-locked loops (ADPLL). However, this approach has several design issues, and the solutions to resolve them always increase the complexity of the system. In this paper, an alternative method for handle the frequency error detection using a type II ADPLL architecture is presented. The proposed technique does not perform direct conversion from time to digital, but employs the discrete-time processing of compared signals from phase error detection. This architecture has the advantage of scalability and integration of all-digital techniques and has less complexity than conventional ADPLLs. The derivation of equations for the proposed architecture and its noise analysis is provided. The results are validated through system level simulations using macro-models of the devices. The result of the transient simulation shows the theoretical predictions about the trajectory of output frequency.