During an at-speed scan-based test, excessive capture power may cause significant current demand, resulting in the IR-drop problem and unnecessary yield loss. Many methods address this problem by reducing the switching activities of power-risky patterns. These methods may not be efficient when the number of power-risky patterns is large or when some of the patterns require extremely high power. In this paper, we propose discarding all power-risky patterns and starting with power-safe patterns only. Our test generation procedure includes two processes, namely, test pattern refinement and low-power test pattern regeneration. The first process is used to refine the power-safe patterns to detect faults originally detected only by power-risky patterns. If some faults are still undetected after this process, the second process is applied to generate new power-safe patterns to detect these faults. The patterns obtained using the proposed procedure are guaranteed to be power-safe for the given power constraints. To the best of our knowledge, this is the first method that refines only the power-safe patterns to address the capture power problem. Experimental results on ISCAS'89 and ITC'99 benchmark circuits show that an average of 75% of faults originally detected only by power-risky patterns can be detected by refining power-safe patterns and that most of the remaining faults can be detected by the low-power test generation process. Furthermore, the required test data volume can be reduced by 12.76% on average with little or no fault coverage loss.

The conventional output compaction methods based on XOR-networks and/or linear feedback shift registers may suffer from the problems of aliasing, unknown-values, and/or poor diagnosability. In this paper, we present an alternative method called the output-bit-selection method to address the test compaction problem. By observing only a subset of output responses, this method can effectively deal with all the above-mentioned problems. Efficient algorithms that can identify near optimum subsets of output bits to cover all detectable faults in very large circuits are developed. Experimental results show that less than 10% of the output response bits of an already very compact test set are enough to achieve 100% single stuck-at fault coverage for most ISCAS benchmark circuits. Even better results are obtained for ITC 99 benchmark circuits as less than 3% of output bits are enough to cover all stuck-at faults in these circuits. The increase ratio of selected bits to cover other types of faults is shown to be quite small if these faults are taken into account during automatic test pattern generation. Furthermore, the diagnosis resolution of this method is almost the same as that achieved by observing all output response bits.

In digital imaging, Moiré patterns pose a significant challenge, appearing as rainbow-colored, warped grid patterns. These artifacts emerge when two overlapping patterns create color distortions due to their slight differences. The limitations of Complementary metal-oxide-semiconductor active pixel sensors become apparent in photos, as these sensors capture information discretely in pixels. This is particularly pronounced when photographing patterned items, mainly due to misalignment issues between the sensor and the regularly spaced, overlapping stripes. This process creates a disparity between real-world continuous lines and digital screens, thereby complicating the work of professional photographers. In response to this challenge, we propose the Demoiréing Multi-Scale Fusion Network (DMSFN). By leveraging dilated-dense attention, multi-scale feature interaction, and multi-kernel strip pooling, our approach effectively detects and removes Moiré patterns from sensor outputs. To enhance the demoiréing performance, we augment the training data by transferring Moiré patterns to clean images. Our experimental results indicate that our proposed model outperforms existing state-of-the-art demoiréing methods, as validated on benchmark datasets. This work contributes to advancing the quality of digital sensor outputs in the presence of Moiré patterns and addressing challenges encountered in practical applications.

This paper proposes an efficient diagnosis-aware ATPG method that can quickly identify equivalent-fault pairs and generate diagnosis patterns for nonequivalent-fault pairs, where an (non)equivalent-fault pair contains two stuck-at faults that are (not) equivalent. A novel fault injection method is developed which allows one to embed all fault pairs undistinguished by the conventional test patterns into a circuit model with only one copy of the original circuit. Each pair of faults to be processed is transformed to a stuck-at fault and all fault pairs can be dealt with by invoking an ordinary ATPG tool for stuck-at faults just once. High efficiency of diagnosis pattern generation can be achieved due to 1) the circuit to be processed is read only once, 2) the data structure for ATPG process is constructed only once, 3) multiple fault pairs can be processed at a time, and 4) only one copy of the original circuit is needed. Experimental results show that this is the first reported work that can achieve 100% diagnosis resolutions for all ISCAS'89 and IWLS'05 benchmark circuits using an ordinary ATPG tool. Furthermore, we also find that the total number of patterns required to deal with all fault pairs in our method is smaller than that of the current state-of-the-art work.

Most underwater image restoration works indicate that restoring images can improve their visual quality and performance of computer vision tasks that use the restored data. This paper aims to investigate how image restoration contributes to underwater object detection. We found that utilizing image restoration through data augmentation rather than using it as a pre-processing step can boost underwater object detection accuracy (up to a 1.9% gain in mAP) on URPC2019 dataset.