This Letter studies the reverse leakage and breakdown mechanisms of vertical GaN-on-Si Schottky barrier diodes (SBDs) with and without argon-implanted termination (ArIT). The electrical leakage characteristics in the vertical GaN-on-Si SBD without edge termination sequentially go through the thermionic field emission, variable range hopping (VRH), and trap-assisted tunneling conduction mechanisms as the reverse bias increases gradually. Its leakage and breakdown mechanisms are limited by the edge electric field crowding effect. While for the vertical GaN-on-Si SBD with ArIT (ArIT-SBD), the electrons conduction at a low reverse bias, following the space-charge-limited conduction (SCLC) model, is limited by the damage-induced traps in the implanted GaN. As the reverse bias increases up to the occurrence of breakdown, the VRH and SCLC dominate the leakage mechanism of the ArIT-SBD, which stem from intrinsic traps in GaN grown on Si. A rapidly growing leakage under a low reverse bias and enhanced breakdown voltage performance in the ArIT-SBD is attributed to the charging of the damage-induced traps in implanted GaN. This Letter not only gives in-depth insights of vertical GaN-on-Si SBDs but also provides a useful design guidance of implanted termination for high-voltage power devices.

A high-performance quasi-vertical GaN Schottky barrier diode (SBD) was successfully fabricated by using a high-quality n ^- -GaN drift layer with a precisely-controlled n-type doping. A high current on/off ratio of 10 ¹⁰ , an ideality factor of 1.03, a low specific on-resistance of 1.41 mΩ·cm ² , and a relatively high breakdown voltage (BV) of 250 V have been achieved for the SBD without edge termination. Furthermore, with an Argon-implanted termination, the as-fabricated GaN-on-Si SBD shows a record high BV of 405 V, yielding a critical electric field of ~ 2 MV/cm, while the forward conduction characteristics are well maintained.

This work demonstrates a novel Nitrogen-implanted (N-implanted) guard ring (GR) technology for the 600-V quasi-vertical GaN-on-Si Schottky barrier diode (SBD). The GR parameters are designed and studied in detail by the TCAD simulation. With a 4.4- $\mu \text{m}$ -thick GaN drift layer, seven GRs with a precise design greatly enhance the breakdown voltage of GaN SBDs from ~290 to ~600 V, and barely degrade the ON-state characteristics, including a high ${I}_{ {\scriptscriptstyle { \mathrm {ON}}}}/{I}_{ {\scriptscriptstyle { \mathrm {OFF}}}}$ of 10 ¹¹ , a low ideality factor of 1.06, a low turn-on voltage of 0.64 V (at 1 A/cm ² ), and a low-specific ON-resistance ( ${R}_{ {\scriptscriptstyle { \mathrm {ON}}},{\mathrm {sp}}}$ ) of 1.40 $\text{m}\Omega ~\cdot ~{\mathrm {cm}}^{2}$ , leading to a record Baliga’s figure of merit (BFOM) of 0.26 GW/cm ² among all the reported vertical GaN-on-Si SBDs. At 175 °C, the SBD with seven GRs shows a slightly increased ${R}_{ {\scriptscriptstyle { \mathrm {ON}}},{\mathrm {sp}}}$ of 1.86 $\text{m}\Omega ~\cdot ~{\mathrm {cm}}^{2}$ and an excellent electrical characteristic even under a reverse bias of 380 V, implying a high-temperature operation capability of N-implanted GRs.

This work reports 1200-V quasi-vertical GaN-on-Si p-n diodes with a 6.6-μm-thick high-quality GaN drift layer showing excellent static and dynamic performance. The as-fabricated GaN-on-Si p-n diode gives a high current on/off ratio of ~10 ¹⁰ , a low ideality factor of 1.2, a low specific on-resistance (R _on,sp ) of 1.3 mΩ∙cm ² , and a high breakdown voltage (BV) of 1210 V. The p-n diode can properly operate at a high temperature of 175 °C, and the device performance can be effectively recovered after the power cycling test. A reduced dynamic on-resistance (R _on ) dependence on the off-state voltage (V _OFF ) and on-state conduction time (T _ON ) is observed in this p-n diode and attributed to the filling dynamics of electron traps. A normalized dynamic R _on of 0.7 is realized after switching from a V _OFF stress at 1000 V. As the first 1200-V GaN-on-Si vertical power device, this cost-effective p-n diode with high performance holds a great promise for high-voltage power applications.

Threshold voltage (V_TH) instability has been studied in the as-fabricated p-GaN gated enhancement-mode high electron mobility transistors (p-GaN E-HEMTs) under a positive gate stress. A negative V_TH shift (ΔV_TH) obtained by dynamic measurement has been observed more severely when compared to the static one. The V_TH deviation is attributed to the complicated influence of carrier transport behaviors in the p-GaN gate. The impacts of hole accumulation, trapping, and consumption on the V_TH instability and drain current variation can be effectively distinguished according to the transfer characteristics obtained from the pulse I–V measurement. Moreover, the density of hole traps in the p-GaN gate is estimated to be around ∼2 × 10¹¹ cm⁻² by the capacitance–voltage measurement, and the energy level is calculated to be around E_V + 0.62 eV by fitting the recovery curve of gate current after positive gate bias. This study focusing on the in-depth influence of different carrier behaviors on the gate performance can help with the understanding and further improvement of the dynamic instability and reliability of the GaN-based HEMTs.