The past decades have witnessed a tremendous development of GaN-based power electronic devices grown on Si substrate. This article provides a concise introduction, review, and outlook of the research developments of GaN-on-Si power device technology. The comprehensive review has discussed the crucial issues in the state-of-the-art device technology based on both GaN materials epitaxy including stress control and point defects study, and device fabrication including normally off solutions like Cascode, trench MIS-gate, and p-GaN gate. Device reliability and other common fabrication issues in GaN high electron mobility transistors (HEMTs) are also discussed. Lastly, we give an outlook on the GaN-on-Si power devices from two aspects, namely high frequency, and high power GaN ICs, and GaN vertical power devices.

Normally-off HEMTs have been fabricated with regrown p-GaN gate and SiN _x passivation by Low-pressure chemical vapor deposition (LPCVD) using an AlN pre-layer, featuring a high-temperature passivation-first technique with no incompatibility issues. Through careful surface treatments, high-quality interfaces (regrown p-GaN/AlGaN and SiN _x /AlGaN), as well as a stable p-GaN contact, can be achieved, enabling a robust gate operation and improved dynamic performance. The as-fabricated device exhibits a low reverse gate leakage of 2 nA/mm @ V _GD = −200 V, a stable forward gate current of $10~\mu \text{A}$ /mm @ V _GS = 5 V, a positive threshold voltage of +1.7 V @ ${I}_{\text {DS}} = {10}\,\,\mu \text{A}$ /mm with a high saturation current of 435 mA/mm, a high I _on /I _off ratio of ${5}\times {10}^{10}$ , and a low R _on,d /R _on,s ratio of 1.5. The as-developed technique with the LPCVD SiN _x passivation and p-GaN gate regrowth may provide a way to enhance the performance of p-GaN E-HEMTs.

In this letter, an enhancement-mode (E-mode) GaN p-channel field-effect transistors (p-FETs) with current density of −5.6 mA/mm and ${I} _{{\mathrm {ON}}}/{I} _{{\mathrm {OFF}}}$ ratio of 10 ⁶ was demonstrated on a p-GaN/AlN/AlGaN/GaN heterostructure on Si substrate. A decent ohmic contact resistivity of $9.25 \times 10^{-5} \Omega \cdot {\mathrm {cm}}^{2}$ is achieved by capping the heterostructure with a 10-nm heavily Mg-doped p ⁺⁺ -GaN epilayer. A two-step gate trench etching process, is implemented to overcome the decreased OFF-state blocking voltage associated with the surface p ⁺⁺ -GaN layer. The proposed structure is compelling for monolithic integration of GaN-based logic and power devices.

This Letter studies the reverse leakage and breakdown mechanisms of vertical GaN-on-Si Schottky barrier diodes (SBDs) with and without argon-implanted termination (ArIT). The electrical leakage characteristics in the vertical GaN-on-Si SBD without edge termination sequentially go through the thermionic field emission, variable range hopping (VRH), and trap-assisted tunneling conduction mechanisms as the reverse bias increases gradually. Its leakage and breakdown mechanisms are limited by the edge electric field crowding effect. While for the vertical GaN-on-Si SBD with ArIT (ArIT-SBD), the electrons conduction at a low reverse bias, following the space-charge-limited conduction (SCLC) model, is limited by the damage-induced traps in the implanted GaN. As the reverse bias increases up to the occurrence of breakdown, the VRH and SCLC dominate the leakage mechanism of the ArIT-SBD, which stem from intrinsic traps in GaN grown on Si. A rapidly growing leakage under a low reverse bias and enhanced breakdown voltage performance in the ArIT-SBD is attributed to the charging of the damage-induced traps in implanted GaN. This Letter not only gives in-depth insights of vertical GaN-on-Si SBDs but also provides a useful design guidance of implanted termination for high-voltage power devices.

A high-performance quasi-vertical GaN Schottky barrier diode (SBD) was successfully fabricated by using a high-quality n ^- -GaN drift layer with a precisely-controlled n-type doping. A high current on/off ratio of 10 ¹⁰ , an ideality factor of 1.03, a low specific on-resistance of 1.41 mΩ·cm ² , and a relatively high breakdown voltage (BV) of 250 V have been achieved for the SBD without edge termination. Furthermore, with an Argon-implanted termination, the as-fabricated GaN-on-Si SBD shows a record high BV of 405 V, yielding a critical electric field of ~ 2 MV/cm, while the forward conduction characteristics are well maintained.

This work demonstrates a novel Nitrogen-implanted (N-implanted) guard ring (GR) technology for the 600-V quasi-vertical GaN-on-Si Schottky barrier diode (SBD). The GR parameters are designed and studied in detail by the TCAD simulation. With a 4.4- $\mu \text{m}$ -thick GaN drift layer, seven GRs with a precise design greatly enhance the breakdown voltage of GaN SBDs from ~290 to ~600 V, and barely degrade the ON-state characteristics, including a high ${I}_{ {\scriptscriptstyle { \mathrm {ON}}}}/{I}_{ {\scriptscriptstyle { \mathrm {OFF}}}}$ of 10 ¹¹ , a low ideality factor of 1.06, a low turn-on voltage of 0.64 V (at 1 A/cm ² ), and a low-specific ON-resistance ( ${R}_{ {\scriptscriptstyle { \mathrm {ON}}},{\mathrm {sp}}}$ ) of 1.40 $\text{m}\Omega ~\cdot ~{\mathrm {cm}}^{2}$ , leading to a record Baliga’s figure of merit (BFOM) of 0.26 GW/cm ² among all the reported vertical GaN-on-Si SBDs. At 175 °C, the SBD with seven GRs shows a slightly increased ${R}_{ {\scriptscriptstyle { \mathrm {ON}}},{\mathrm {sp}}}$ of 1.86 $\text{m}\Omega ~\cdot ~{\mathrm {cm}}^{2}$ and an excellent electrical characteristic even under a reverse bias of 380 V, implying a high-temperature operation capability of N-implanted GRs.