By exploiting the rich automorphisms of Reed–Muller (RM) codes, the recently developed automorphism ensemble (AE) successive cancellation (SC) decoder achieves a near-maximum-likelihood (ML) performance for short block lengths. However, the appealing performance of AE-SC decoding arises from the diversity gain that requires a list of SC decoding attempts, which results in a high decoding complexity. To address this issue, this paper proposes a novel quasi-optimal path convergence (QOPC)-aided early termination (ET) technique for AE-SC decoding. This technique detects strong convergence between the partial path metrics (PPMs) of SC constituent decoders to reliably identify the optimal decoding path at runtime. When the QOPC-based ET criterion is satisfied during the AE-SC decoding, only the identified path is allowed to proceed for a complete codeword estimate, while the remaining paths are terminated early. The numerical results demonstrated that for medium-to-high-rate RM codes in the short-length regime, the proposed QOPC-aided ET method incurred negligible performance loss when applied to fully parallel AE-SC decoding. Meanwhile, it achieved a complexity reduction that ranged from 35.9% to 47.4% at a target block error rate (BLER) of ${10}^{-3}$, where it consistently outperformed a state-of-the-art path metric threshold (PMT)-aided ET method. Additionally, under a partially parallel framework of AE-SC decoding, the proposed QOPC-aided ET method achieved a greater complexity reduction that ranged from 81.3% to 86.7% at a low BLER that approached ${10}^{-5}$ while maintaining a near-ML decoding performance.

In the context of certain specific digital communication systems, where there are limitations such as spectral resources and energy availability, continuous phase modulation (CPM) emerges as an appealing choice among various modulation methods. Among CPM signals, multi‐h CPM is particularly noteworthy for its ability to address these constraints within the realm of single‐carrier and constant‐envelope waveforms. At the physical layer, the design of a multi‐h CPM receiver necessitates the efficient implementation of timing and frequency synchronization algorithm within a high dynamic environment. So this paper presents an innovative approach for achieving timing and frequency synchronization. To rectify timing offset and mitigate the adverse effects of noise in received signals, a re‐configurable local filter generation method is integrated into the timing synchronization algorithm. Simultaneously, an enhanced least mean square adaptive filter algorithm is applied to address frequency synchronization. A comprehensive series of simulations rigorously evaluates the outcomes of proposed novel synchronization methodology. These analyses demonstrate a notable proximity between the synchronization errors of proposed algorithm in this paper and the performance benchmark set by the modified Cramer–Rao bound. The proposed synchronization technology also exhibits the capability to substantially reduce the bit error rate, thereby effectively enhancing demodulation performance in multi‐h CPM receivers.

The BeiDou-3 system is an independently developed and autonomously operated global navigation system in China, offering three fundamental services through its short message communication capabilities: location reporting, emergency search and rescue, and message communication. The undistorted reception of BeiDou short message information by a BeiDou short message receiver plays a crucial role in the implementation of BeiDou short message services. BeiDou short messages are divided into global short messages and region short messages, with significant differences in their spreading spectrum method. Hence, the research on a universal BeiDou short message receiver holds significant importance. In response to the distinct spreading spectrum method employed for global short messages and region short messages, this paper designs a universal Beidou short message receiver based on FPGA. By introducing a short message data caching module that controls the acquisition timing, it achieves rapid and effective acquisition of both global and region short messages. Furthermore, the functionality provided by the tracking loop and pseudocode switching controller module ensures continuous and stable tracking of both global and region short messages. Xilinx’s xc7z100ffg900-2 chip was used for simulation and actual testing, which verified that the designed Beidou short message universal receiver can receive global short messages and region short messages without distortion.

Multiple Phase Shift Keying (MPSK) and Multiple Amplitude Phase Shift Keying (MAPSK) represent widely adopted modulation techniques in satellite communications, primarily due to their characteristic of low peak-to-average ratio. However, the rapid mobility of satellites induces substantial Doppler frequency shifts, which poses formidable challenges for carrier synchronization in coherent receivers. Consequently, this paper presents a carrier synchronization algorithm based on the Attached SYNC Marker (ASM). The proposed approach leverages the ASM embedded within the data frame structure as prior knowledge to estimate the carrier error and correct the local oscillator. Considering that the Doppler frequency offset may significantly exceed the estimated range, the Low Density Parity Check (LDPC) code syndrome check is employed to facilitate the determination of Doppler frequency. The experimental results confirm that the frequency estimation error is a few hundred hertz, the phase estimation error is around 0.1, and the maximum bit error rate (BER) performance loss is approximately 0.5dB. These results substantiate the effectiveness of proposed method in carrier synchronization for MPSK and MAPSK signals.

The Multiple Symbol Detection (MSD) algorithm can effectively lower the demodulation threshold in Frequency Modulation (FM) technology, which is widely used in aircraft wireless communications due to its insensitivity to large Doppler shifts. However, the high computational complexity of the MSD algorithm leads to considerable hardware resource overhead. In this paper, we propose a novel MSD architecture based on hybrid stochastic computing (SC), which allows for accurate signal detection while maintaining low hardware complexity. Given that the correlation calculation dominates the computational load in the MSD algorithm, we develop an SC-based, low-complexity unit to perform complex correlation operations using simple hardware circuits, significantly reducing the hardware overhead. Particularly, we integrate a flexible and scalable stochastic adder in the SC-based correlation calculation, which incorporates an adjustable scaling factor to enable high distinguishability in all possible correlation results. Additionally, for the symbol decision process of the MSD algorithm, we design a binary computing-based pipeline architecture to execute the computing process serially, which leverages the inherent low update rate of SC-based correlation results to further reduce the overall resource overhead. Experimental results show that, compared to an 8-bit quantization MSD implementation, our proposed hybrid SC-based MSD architecture achieves a comparable bit error rate while reducing the hardware resources to 69%, 45%, and 36% of those required for the three-, five-, and seven-symbol MSD algorithms, respectively.