The set-up for a new electrical system for variable renewable energy resources (RERs) will bring additional capital costs and therefore upgradation of the existing systems is by far the best option to ensure little to no greenhouse gases (GHGs) or harmful pollutants. This paper reports advanced power electronic converter-based devices (PECs) which play a crucial role in conversion and control activities in connecting RERs to power grids they cannot only bypass the associated challenges but can also be an efficient and potential equipment in power and energy sector. The interfacing of PECs with RERs is explored in this work is powered by an advanced framework in which smart inverters (SIs) are also utilized to maintain the regulated output voltage in line with the grid requirement and the effectiveness of the developed system is verified on MATLAB environment. The capabilities of SIs are emphasized which ranges from enhanced coordination between the devices, better efficiency and seamless integration of renewables with the utility grid to ensure holistic operation. A detailed analysis is performed and the outcomes reveal the suitability and applicability of the proposed work and in particular, interfacing PECs with the utility grid not only improves the performance of the system but also increases efficiency and limits the challenges associated with the integration of renewables in the mainstream grid to a considerable extent. The peak voltage of 300 V is produced by employing SIs from solar PV system which corresponds to an RMS voltage of 212.13 V within the permissible frequency range.

Addition is one of the most fundamental arithmetic operations. Any adder in a digital circuit and system can improve the digital system's performance. Adders, for example, are commonly found in the critical path of many ALUs, processors, and digital signal processing chips. As a result, each of these blocks should execute efficiently and precisely on their own, enhancing the overall performance of the system. Optimizing an adder may lead to overall system optimization. A desirable adder meets all the criteria, such as high speed, low-power dissipation, low leakage power, and small footprint. However, because there is a trade-off between the area, power and, speed.Obtaining the finest adder in terms of speed, power dissipation, leakage power, and area consumed would assist the designer in selecting an adder for the given application. Transmission function adder (TFA), 17-transistor adder (17-TA), 14-transistor adder (14-TA), ripple carry adder (RCA), carry lookahead adder (CLA), and carry-select adder are among the new 2-bit adders suggested and compared (CSL). This research presents a comparative analysis and performance evaluation of adders based on latency, power dissipation, PDP, leakage power, area, and EDP. Simulations are being done using HSPICE software at 28-nm technology with a supply voltage range of 0.7–1.1 V. The suggested adder has a minimum delay and is 8.6% faster than CLA, according to simulation results. When compared to the other adders, it uses the minimum area and has the lowest leakage power. The proposed adder has minimum power delay product.