In this paper, a "composite" source-follower is presented. Using a positive-feedback, the structure synthesizes complex poles with a single branch. This allows to realize a single-branch biquadratic cell. Moreover, due to the intrinsic feedback present in any source-follower, the proposed cell performs larger linearity for smaller V_ov(=V_GS-V_TH). This is the opposite of other active filters and allows saving the power otherwise used to increase linearity. A fourth-order prototype satisfy typical WLAN 802.11.a/b/g baseband filter specifications has been realized in a 0.18 mum CMOS at 1.8-V supply. It achieves a 17.5-dBm IIP3 and a -40 dB HD3 for a 600-mV_{pp_diff} input signal amplitude. A 24-muV_rms noise gives a DR=79 dB, with 2.25-mA current consumption

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/performance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-mum CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 muVrms and 163 muVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

In this paper, a 4th-order low-pass continuous-time analog filter is presented, that is implemented with the cascade of two efficient and compact biquadratic cells, realized using the Super-Source-Follower topology. The biquadratic cell uses only two capacitors and four transistors: two transistors for the signal processing and two transistors as current sources for biasing purpose. The 4th-order filter prototype has been integrated in 0.18 μm CMOS technology. For a 33 MHz cut-off frequency, the filter performs 18 dBm-IIP3 for two tones at 2 MHz and 3 MHz, with total current of 770 μA from a single 1.8 V supply voltage.

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two active- G_m-RC biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The - 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The -3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 mum CMOS technology with V_THN ap 0.25 V and V_THP ap 0.3 V, the filter operates with a supply voltage as low as 0.55 V. The filter (total area=0.47 mm²) consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1-5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 mum CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate.