Dr. Marcello De Matteis

Alessandro Pezzotta

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

In this paper, a 4th-order low-pass continuous-time analog filter is presented, that is implemented with the cascade of two efficient and compact biquadratic cells, realized using the Super-Source-Follower topology. The biquadratic cell uses only two capacitors and four transistors: two transistors for the signal processing and two transistors as current sources for biasing purpose. The 4th-order filter prototype has been integrated in 0.18 μm CMOS technology. For a 33 MHz cut-off frequency, the filter performs 18 dBm-IIP3 for two tones at 2 MHz and 3 MHz, with total current of 770 μA from a single 1.8 V supply voltage.

28 August 2009 in IEEE Journal of Solid-State Circuits

Journal Article

CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two active- G_m-RC biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The - 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The -3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 mum CMOS technology with V_THN ap 0.25 V and V_THP ap 0.3 V, the filter operates with a supply voltage as low as 0.55 V. The filter (total area=0.47 mm²) consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.

1 November 2012 in Journal of Instrumentation

Journal Article

M Maino

G Pessina

26 September 2011 in IEEE Transactions on Circuits and Systems I: Regular Papers

Journal Article

A 255 MHz Programmable Gain Amplifier and Low-Pass Filter for Ultra Low Power Impulse-Radio UWB Receivers

Marco De Blasi

A Biquadratic Cell Based on the Flipped-Source-Follower Circuit

A 90 nm-CMOS power-optimized analog baseband chain for ultra-low-power impulse-radio ultra-wideband (IR-UWB) receivers is presented. The proposed device merges the functions of a programmable gain amplifier (PGA) and a low-pass filter (LPF). It consists of the cascade of three biquadratic cells made up by opamps in a series-shunt configuration, which features high input impedance, low load effects in the cascade blocks, and better frequency response. The opamp parameters are included in the overall biquad transfer function. This allows getting very low power performance, since the opamp bandwidth is not required to be much larger than the filter cutoff frequency. Moreover, the current consumption is optimized according to the selected gain level (1.3 mA at 0 dB-gain up to 1.9 mA at 40 dB-gain). The PGA features a 0-40 dB programmable gain range with a 5 dB gain-step. The LPF performs a sixth-order 255 MHz low-pass frequency response. For the overall chain the IIP3 is 14 dBm at 0 dB gain, while the input referred noise is 12.5 nV/√Hz at 40 dB gain.

19 September 2016 in IEEE Transactions on Circuits and Systems II: Express Briefs

Journal Article

A 7.65-mW 5-bit 90-nm 1-Gs/s Folded Interpolated ADC Without Calibration

Andrea Baschirotto

This paper presents a novel biquadratic cell (biquad) based on the Flipped-Source-Follower (FSF) circuit. The main idea is to exploit the FSF circuit as basic building block for a lowpass 2nd-order filter, taking advantage of its well known strengths, like low output impedance, low-noise, large in-band linearity, and low-power. Thanks to the very essential FSF circuit, the resulting biquad is a power efficient broad bandwidth stage, with very low-noise performance. In order to validate the biquadratic cell design idea, extensive circuital simulation results will be presented. The filter design example synthesizes a 3rd-order low-pass transfer function and consumes 2.3mW from a single 1.8V@V $_{DD}$ . Input noise spectral density is 7nV/√Hz. Linearity has been evaluated in terms of IIP3 (25dBm) and THD (-40dBc at 380mV $_{0-PEAK}$ output voltage swing, resulting in 62dB SNR). Hence a very promising Figure-of-Merit (i.e. 165J-1) has been achieved.

30 August 2013 in IEEE Transactions on Instrumentation and Measurement

Journal Article

Giuseppe Cocciolo

Annachiara Spagnolo