This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed set of blocks takes into account most of the SC /spl Sigma//spl Delta/ modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC /spl Sigma//spl Delta/ modulator.

In this paper, a "composite" source-follower is presented. Using a positive-feedback, the structure synthesizes complex poles with a single branch. This allows to realize a single-branch biquadratic cell. Moreover, due to the intrinsic feedback present in any source-follower, the proposed cell performs larger linearity for smaller V_ov(=V_GS-V_TH). This is the opposite of other active filters and allows saving the power otherwise used to increase linearity. A fourth-order prototype satisfy typical WLAN 802.11.a/b/g baseband filter specifications has been realized in a 0.18 mum CMOS at 1.8-V supply. It achieves a 17.5-dBm IIP3 and a -40 dB HD3 for a 600-mV_{pp_diff} input signal amplitude. A 24-muV_rms noise gives a DR=79 dB, with 2.25-mA current consumption

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/performance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-mum CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 muVrms and 163 muVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.