DC and 1/f noise performances of the AlGaN/GaN fin-shaped field-effect transistor (FinFET) with fin width of 50 nm were analyzed. The FinFET exhibited approximately six times larger normalized drain current and transconductance, compared to those of the AlGaN/GaN planar metal-insulator-semiconductor heterostructure field-effect-transistor (MISHFET) fabricated on the same wafer. It was also observed that the FinFET exhibited improved noise performance with lower noise magnitude of 8.5×10 ^-15 A ² /Hz when compared to the value of 8.7×10 ^-14 A ² /Hz for the planar MISHFET. An intensive analysis indicated that both devices follow the carrier number fluctuation model, but the FinFET suffers much less charge trapping effect compared to the MISHFET (two orders lower charge trapping was observed). Moreover, the FinFET did not exhibit the Lorentz-like components, which explains that the depleted fin structure effectively prevents the carriers from being trapped into the underlying thick GaN buffer layer. On the other hand, the slope of the noise is 2 irrespective of drain voltage and apparently showed the Lorentz-like components, especially at high drain voltage in MISHFET device. This explains that the carrier trapping/detrapping between the 2-D electron gas channel and the GaN buffer layer is significant in MISHFET.

The low-frequency noise (LFN) characteristics of AlGaN/GaN FinFETs with omega-gate and combined two-dimensional electron gas (2DEG) and MOS conduction are investigated. It is found that LFN is dominated by carrier number fluctuations whatever the width of the fin. Charge trapping in narrow devices is one order of magnitude lower than in wide fin device. In narrow devices, the sidewall conduction prevails and the noise mainly stems from the carrier trapping in the sidewall Al2O3 gate dielectric. Instead, in wide fin devices, the top gate AlGaN/GaN HEMT structure dominates and the LFN is mostly governed by the carrier trapping in the GaN layer close to 2DEG channel.

Using capacitance, conductance and noise measurements, we investigate the trapping behavior at the surface and in the core of triangular-shaped one-dimensional (1D) array of GaN nanowire gate-all-around field effect transistor (GAA FET), fabricated via a top-down process. The surface traps in such a low dimensional device play a crucial role in determining the device performance. The estimated surface trap density rapidly decreases with increasing frequency, ranging from 6.07 × 10¹² cm⁻²·eV⁻¹ at 1 kHz to 1.90 × 10¹¹ cm⁻²·eV⁻¹ at 1 MHz, respectively. The noise results reveal that the power spectral density increases with gate voltage and clearly exhibits 1/f-noise signature in the accumulation region (V_gs > V_th = 3.4 V) for all frquencies. In the surface depletion region (1.5 V < V_gs < V_th), the device is governed by 1/f at lower frequencies and 1/f² noise at frequencies higher than ~ 5 kHz. The 1/f² noise characteristics is attributed to additional generation–recombination (G–R), mostly caused by the electron trapping/detrapping process through deep traps located in the surface depletion region of the nanowire. The cutoff frequency for the 1/f² noise characteristics further shifts to lower frequency of 10²–10³ Hz when the device operates in deep-subthreshold region (V_gs < 1.5 V). In this regime, the electron trapping/detrapping process through deep traps expands into the totally depleted nanowire core and the G–R noise prevails in the entire nanowire channel. Open image in new window

We investigated the performances of GaN junctionless fin-shaped field-effect transistors (FinFETs) with two different types of gate structures; overlapped-and partially covered-gate. DC, low-frequency noise (LFN), and pulsed I-V characterization measurements were performed and analyzed together in order to identify the conduction mechanism and examine both the interface and buffer traps in the devices. The fabricated GaN junctionless device with overlapped-gate structure exhibits improved DC and noise performance compared to the device with partially covered-gate, even though its gate length is much larger. The LFN behavior was found to be dominated by carrier number fluctuations (CNF). At off-state, the device with partially covered-gate exhibits generation-recombination (g-r) noise on top of 1/f noise. This superposition is correlated with the severe current collapse revealed by pulsed I-V measurements. In contrast, the device with overlapped-gate shows clear 1/f behavior without g-r noise.

This paper presents a new concept, supported by 3-D TCAD simulations, for improving the performance and subthreshold swing (SS) of enhancement-mode AlGaN/GaN fin-shaped field-effect transistors (FinFETs). By choosing appropriate device parameters, the formation of 2-D electron gas (2DEG) can be delayed such as to ensure simultaneous activation of 2DEG and sidewall MOS channels at positive threshold voltage for normally off operation. The 2DEG channel starts forming in the middle of the fin, whereas the edges are depleted by the lateral MOS gates. Not only increasing the gate voltage does the 2DEG charge increase, but also the effective width is enlarged being less depleted by the gates. This double-2DEG mechanism adds to the regular MOS channels on the sidewalls and enables enhanced performance. The 3-D TCAD simulations indicate that narrow FinFET (20 nm) can exhibit excellent switching characteristics: very low SS of 55 mV/decade, below the 60 mV/decade limit, high on/off current ratio of 10 ¹⁰ , and good current driving capability due to the added 2DEG channel contribution. The maximum transconductance is 350 mS/mm, the drain current reaches 380 mA/mm, and the on resistance is as low as 0.018 mΩ · cm ² .