This paper presents a new modeling and simulation method to predict the important statistical performance of single photon avalanche diode (SPAD) detectors, including photon detection efficiency (PDE), dark count rate (DCR) and afterpulsing probability (AP). Three local electric field models are derived for the PDE, DCR and AP calculations, which show analytical dependence of key parameters such as avalanche triggering probability, impact ionization rate and electric field distributions that can be directly obtained from Geiger mode Technology Computer Aided Design (TCAD) simulation. The model calculation results are proven to be in good agreement with the reported experimental data in the open literature, suggesting that the proposed modeling and simulation method is very suitable for the prediction of SPAD statistical performance.

Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ±2 mT magnetic field and output a digital Hall signal in a wide temperature range from −40 °C to 120 °C.

An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature.

A compact high-speed active quenching and recharging circuit (AQRC) is proposed for single-photon avalanche diode (SPAD) detectors fabricated in standard 0.18 μm CMOS technology. A novel sensing and quenching scheme is employed to speed up the process of avalanche detection, enabling a low afterpulsing probability and a high photon-counting rate. The simulation and experimental results indicate that the sensing and quenching time is reduced down to 0.7 ns and the maximum photon-counting rate is close to 200 Mcps (counts per second), meanwhile the afterpulsing probability as low as 0.75% is obtained. Due to the compact configuration, the area occupation of the AQRC is only 306 μm2. Such outstanding advantages suggest that the proposed AQRC is very suitable for the miniaturized and high-speed SPAD-array detectors.

Multi-frequency Terahertz (THz) detectors have shown great application potentials in THz imaging and sensing systems. For the first time to our knowledge, a novel dual-frequency THz detector with the stacked structure consisting of a silicon-based plasmonic antenna and a metal-based antenna in one compact unit is proposed and fabricated in standard CMOS technology. Compared with the metal antenna, the antenna based on heavy-doped poly-silicon materials enables the detector to excite localized surface plasmon resonance mode, making the effective absorption of the THz waves and thus resulting in the significant responsivity enhancement of the detector. The experimental results show a maximum voltage responsivity up to about 2000 V/W and 450 V/W, while the noise equivalence power is as low as 23 pW/Hz0.5 and 110 pW/Hz0.5 for the silicon antenna and metal antenna at the frequency of 220 GHz and 650 GHz, respectively. The presented dual-frequency detector can be easily implemented in a small size in favor of high-density array integration.

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.