Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) design. The surrogate has three main components: a set of Gaussian process regression models of the technology’s parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs. The proposed surrogate is $69X$ to $470X$ faster at evaluation compared with circuit simulations.

Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in ${\mathrm{P}}_{1\mathrm{dB}}$ in the multi-loop implementation with respect to the single-loop case.

Automatic and flexible analog integrated circuit design is still an open topic. Simulation-based optimization is accurate but relies on the efficacy of heuristics to find a solution. Equation-based optimization is faster, can work with both gradients and heuristic algorithms but the accuracy depends on the set of equations. We propose an equation-based surrogate model that combines physics-based transistor model, curve fitting approximations for device parameters, and circuit analysis describing the metrics of the circuit to optimize. Two design examples are provided as proof of concept of the proposed optimization framework, a 2nd-order active-RC Butterworth filter, and a Capless-LDO. The results prove this technique to be effective finding solutions for different processes technologies and flexible to the specifications. Multi-objective optimization is used to generate a Pareto front representing the design trade-off.

In this paper a method to reduce the harmonic distortion caused by the switching operation in switched-R-MOSFET-C filters is presented. The technique is demonstrated through simulations and backed by analytical expressions for first order active RC and second order biquad filters; the improvement in clock distortion is presented and compared with previously reported architectures. The proposed harmonic cancellation technique shows an improvement of more than 33 dB over previous architectures without compromising the tuning range.