Multistage amplifiers are a reliable method of achieving high gain in systems where the voltage supply is low. The common practice is to prefer 3-stage amplifiers over 4-stage ones when a gain of 1.18 MGz and a phase margin (PM) of > 48° for all drivable load values. The proposed design, implemented in a standard CMOS 130-nm process, can drive a wide range of load capacitors without sacrificing any aspect of performance.

Since operational transconductance amplifiers (OTAs) form the basic building blocks of many analog systems, the compensation of three-stage OTAs has attracted a lot of attention in the literature. Many different solutions to the stability problem of such OTAs have been proposed over the past 20 years, with each solution exhibiting different properties or targeting a different application. This work surveys a broad selection of previously reported architectures and proposes a novel classification scheme that exposes features common to seemingly different compensation architectures and serves as a guideline for which type of OTA is suitable for a given application. In addition, a novel figure of merit (FoM) is proposed to guide the designer in deciding which OTA architecture suits the tradeoffs specific to the application at hand. Theoretical discussions are further reinforced by transistor-level simulation results.

With the aggressive scaling of transistor dimensions, intrinsic device gains are dropping but the need for high-gain amplifiers still exists, resulting in a great interest in multi-stage amplifiers. Most existing amplifier topologies rely on Miller capacitors which achieve stability at the expense of reduced speed. In this paper, a new state feedback compensation strategy with gain enhancement using partial positive feedback is proposed whereby a multistage amplifier can be made output-compensated, thereby requiring no Miller capacitance while being able to drive a wide range of load capacitances. After a thorough theoretical analysis, a topology prototype is fabricated in a standard 130 nm CMOS technology and is able to drive loads from 90 nF-50 nF (~555x) using three discrete modes. The amplifier's power and bandwidth are scalable depending on the expected capacitive load range, with a maximum power consumption of (185μW) from a 1V supply. Comparison with state-of-the-art amplifiers shows superior small-signal performance and competitive large-signal performance while driving a significantly larger range of capacitive loads.

Integrating multiple on-chip voltage regulators in a power delivery network (PDN) can offer promising improvements in both voltage regulation and power efficiency. However, the complex interactions between active regulators and the surrounding parasitic passive network create a large number of feedback loops and thus cause stability concern for the distributed regulation network. The recently emerged PDN design methodology based on the hybrid stability theory (HST) provides a unique opportunity for taming the complex PDN stability problem. However, the HST-based stability margin is unfamiliar to circuit designers, and therefore stability-constrained design intuitions are derivable. In this brief, our systematic analysis reveals unique design considerations which can significantly impact the system-level stability and performances. Within a large design space, a comprehensive set of design studies are conducted to shed light on the tradeoffs between the HST-based stability margin and other PDN design specifications such as the quiescent current consumption, maximum switching noise, and area overhead. Useful design insights like how regulator topology, passive decoupling capacitance, and the number of on-chip regulators may be optimized for improved tradeoffs between stability and system performance are discussed. These insights can aid circuit designers to make appropriate design choices at the beginning of the design process for improved system tradeoffs.

Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in ${\mathrm{P}}_{1\mathrm{dB}}$ in the multi-loop implementation with respect to the single-loop case.

A major challenge currently facing integrated systems, such as microprocessors and systems-on-chip is power delivery. With increasing system size and complexity, multiple voltage regulators are often needed for a single power domain. This connection raises non-trivial stability issues that often render the system useless. It is therefore of great practical interest to tackle the stability of such systems. This brief proposes the design of a centralized controller with the aim of rendering such power delivery networks (PDNs) stable without compromising their performance. Theoretical results are confirmed with extensive transistor-level simulations and demonstrate that the controller is capable of stabilizing PDNs with much greater area efficiency than conventional techniques.