Even though the hysteresis in the gate transfer characteristics of two-dimensional (2D) transistors is a frequently encountered phenomenon, the physics behind it are up to now only barely understood, let alone modeled. Here, we demonstrate that the hysteresis phenomenon can be captured accurately by a previously established non-radiative multiphonon model describing charge capture and emission events in the surrounding dielectrics. The charge transfer model is embedded into a drift-diffusion based TCAD simulation environment, which was adapted to 2D devices. Our modeling setup was validated against measurement data on a back-gated single-layer MoS ₂ transistor with SiO ₂ as a gate dielectric. We use the modeling approach to gain a thorough understanding of the hysteresis, which will help to control this problem in future devices.

Defects in the gate oxide give rise to bias temperature instability (BTI), which is considered a serious threat to the device reliability of ultrascaled MOSFETs. Extrapolating the device degradation over the operational lifetime, therefore, requires detailed knowledge about the distributions of defects causing BTI. Typically, BTI degradation is modeled by calibrating a predefined defect parameter distribution, such as normally distributed defect bands, by employing measure-stress-measure (MSM) sequences at various temperatures. Here, we present the Effective Single Defect Decomposition (ESiD), a novel method for a semiautomated extraction of defect parameters from MSM experiments which does not require any prior assumptions about their distributions . This technique decomposes the MSM sequences into contributions from dominant effective single-defects and constructs a defect parameter distribution that reproduces the experimental data with high accuracy. We validate this new method by comparing its results to density functional theory (DFT) predictions and single-defect characterizations.

Leakage currents through dielectrics in modern logic, memory, and power devices, and back-end interlevel layers can severely increase the time-zero power dissipation and shorten the lifetime of the material structure. Depending on thickness, material properties, and fabrication quality, different conduction mechanisms through the insulating layer, such as band-to-band and trap-assisted tunneling (TAT) are observed. These leakage currents can be distinguished by their dependence on electric field strength, temperature, and their transient characteristics. The identification of the underlying mechanisms is of utmost importance for the selection of suitable dielectrics and optimization of device processing. In this work, we present a nonradiative multiphonon model which extends our compact physics (Comphy) reliability framework to also account for TAT. The model is based on a single physical defect parameter set from which charge transfer kinetics between charge carrier reservoirs and oxide defects (single-TAT) as well as between the defects (multi-TAT) can be derived. We thereby demonstrate that the thermal barrier for inelastic defect–defect carrier tunneling is approximately twice as large in comparison to reservoir-defect interaction and further show in which parameter regime multi-TAT plays a role. Our results show that multi-TAT currents are a less important contribution to the overall tunnel current than previously assumed.

Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is typically beneficial for their operating characteristics, such as switching speed and power consumption, but at the same time miniaturization also leads to increased variability among nominally identical devices. Adverse effects due to oxide traps in particular become a serious issue for device performance and reliability. While the average number of defects per device is lower for scaled devices, the impact of the oxide defects is significantly more pronounced than in large area transistors. This combination enables the investigation of charge transitions of single defects. In this study, we perform random telegraph noise (RTN) measurements on about 300 devices to statistically characterize oxide defects in a Si/SiO ${}_2$ technology. To extract the noise parameters from the measurements, we make use of the Canny edge detector. From the data, we obtain distributions of the step heights of defects, i.e., their impact on the threshold voltage of the devices. Detailed measurements of a subset of the defects further allow us to extract their vertical position in the oxide and their trap level using both analytical estimations and full numerical simulations. Contrary to published literature data, we observe a bimodal distribution of step heights, while the extracted distribution of trap levels agrees well with recent studies.