Defects in the gate oxide give rise to bias temperature instability (BTI), which is considered a serious threat to the device reliability of ultrascaled MOSFETs. Extrapolating the device degradation over the operational lifetime, therefore, requires detailed knowledge about the distributions of defects causing BTI. Typically, BTI degradation is modeled by calibrating a predefined defect parameter distribution, such as normally distributed defect bands, by employing measure-stress-measure (MSM) sequences at various temperatures. Here, we present the Effective Single Defect Decomposition (ESiD), a novel method for a semiautomated extraction of defect parameters from MSM experiments which does not require any prior assumptions about their distributions . This technique decomposes the MSM sequences into contributions from dominant effective single-defects and constructs a defect parameter distribution that reproduces the experimental data with high accuracy. We validate this new method by comparing its results to density functional theory (DFT) predictions and single-defect characterizations.

In the context of renewable energy generation, compact and efficient electric power conversion is becoming increasingly important. Due to their low-loss switching capability at high frequencies, of up to hundreds of kilohertz, silicon carbide (SiC) MOSFETs are currently gaining a lot of attention from industry and are gradually replacing silicon (Si)-based devices in numerous applications. Recently, it has been revealed that SiC MOSFETs show a new type of instability in extensive high-frequency operations when the device is switched in bipolar mode. This gate switching instability has been observed in all commercial devices and occurs concurrently with the well-known bias temperature instability. We summarize the defining experimental characteristics of gate switching instability, including frequency, voltage, temperature, transition time dependencies, and the impact of undershoots in gate voltage. Subsequently, we discuss these observations together with those from other researchers, including recently proposed mechanisms and how they agree or disagree with the available experimental evidence. In the second part of this publication, we will present a detailed physics-based model that fully agrees with all presented experiments.

Silicon carbide (SiC) MOSFETs still exhibit higher drifts of the threshold voltage than comparable silicon devices due to charge trapping, especially regarding small time scales. Understanding this behavior and the consequences in application relevant conditions is therefore of high research interest. Since charge trapping at different defects close to the SiC/ SiO ₂ interface and in the bulk oxide is strong bias and temperature-dependent, the phenomenon is referred to as bias temperature instability (BTI). It has been shown that drifts caused by BTI vary both in transient shape and magnitude for commercially available devices. These differences arise from defect densities and properties in the respective technologies. A physical model together with defect parameters that explain the charge transfer reactions at the defects is essential to understand all peculiarities of the transient degradation. In this work, we use a novel method to semiautomatically extract defect parameters within a two-state nonradiative multiphonon model framework. Our work reveals properties of defects responsible for shifts of the threshold voltage for both short-term ac and long-term dc stress conditions which are accurately reproduced for three different DMOS technologies. Our calibrated simulation framework is further used to extrapolate device degradation at operation relevant ac bias conditions to typical device lifetimes.

Two-dimensional materials have been widely investigated to implement memristive devices for data storage or neuromorphic computing applications because of their ultra-scaled thicknesses and clean interfaces. For example, resistance switching in hexagonal boron nitride (h-BN) has been demonstrated. This mechanism is most of the time attributed to the movement of metallic ions. It has however also been reported when h-BN is contacted with two inert electrodes such as graphene or Pt. We suggest here that the switching mechanism of the latter devices, which has not yet been clearly established, relies on locals change of the electronic structure of h-BN as caused by atomic defects, e.g., multi-vacancies. This class of intrinsic h-BN defects can create electrically controllable interlayer bridges. We use a combination of hybrid density functional theory and the Non-equilibrium Green’s function formalism to show that a single interlayer bridge resulting from the presence of a trivacancy in a graphene/h-BN/graphene stack leads to a switching voltage of ~5 V and a high-to-low resistance ratio >100. Both values lie within the reported experimental range and thus confirm the likelihood that intrinsic defects play a key role in the resistance switching of h-BN in contact with inert electrodes.