Negative capacitance FETs with channel lengths from 30 nm to 50 um, gated with ferroelectric hafnium zirconium oxide are fabricated on Fully Depleted Silicon-on-Insulator (FDSOI) substrates. Enhanced capacitance due to negative capacitance, hysteresis-free operation and improved subthreshold slope are observed. The negative capacitance effect leads to enhancement of drain current for small voltage operation. In addition, improved short channel performance is demonstrated owing to the reverse DIBL characteristics of the negative capacitance operation.

We report on negative capacitance FETs (NCFET) with 1.8 nm thick Zr-doped HfO2 gate oxide layer, fabricated on a FDSOI wafer. Hysteresis-free operation is demonstrated. When compared to a baseline that uses HfO2 gate oxide with the same thickness, a subthreshold swing (SS) steeper by more than 20mV/decade and larger than 10X reduction in the OFF current (IOFF) is observed at 30nm channel length, at a constant ION. On the other hand, at matched IOFF, NCFET provides a larger ON current at constant VDD. Our results indicate that the beneficial characteristic offered by NCFETs can be obtained at scaled channel lengths, while using oxide layers whose thickness is comparable to the high-K oxide layer used in ultra-scaled nodes.

Analog reservoir computing (ARC) systems have attracted attention owing to their efficiency in processing temporal information. However, the distinct functionalities of the system components pose challenges for hardware implementation. Herein, we report a fully integrated ARC system that leverages material versatility of the ferroelectric-to-mixed phase boundary (MPB) hafnium zirconium oxides integrated onto indium–gallium–zinc oxide thin-film transistors (TFTs). MPB-based TFTs (MPBTFTs) with nonlinear short-term memory characteristics are utilized for physical reservoirs and artificial neuron, while nonvolatile ferroelectric TFTs mimic synaptic behavior for readout networks. Furthermore, double-gate configuration of MPBTFTs enhances reservoir state differentiation and state expansion for physical reservoir and processes both excitatory and inhibitory pulses for neuronal functionality with minimal hardware burden. The seamless integration of ARC components on a single wafer executes complex real-world time-series predictions with a low normalized root mean squared error of 0.28. The material-device co-optimization proposed in this study paves the way for the development of area- and energy-efficient ARC systems.

Wakeup-free and endurance-robust HfZrO2 (HZO) ferroelectric field-effect transistor (FeFET) was fabricated on a silicon-on-insulator substrate. After a high-pressure forming gas annealing as the last alloy step, the performance and endurance of the FeFETs were significantly improved by trap states reduction, polarization enhancement, and wake-up elimination. As the result, the FeFETs show superior endurance exceeding 1010 cycles and robust retention behavior at program/erase biases of ±3.5V and pulse width of 100 ns. These results indicate that appropriate thermal treatment for the interlayer and ferroelectric material could substantially improve FeFET performance and reliability.

With the recently increasing prevalence of deep learning, both academia and industry exhibit substantial interest in neuromorphic computing, which mimics the functional and structural features of the human brain. To realize neuromorphic computing, an energy‐efficient and reliable artificial synapse must be developed. In this study, the synaptic ferroelectric field‐effect‐transistor (FeFET) array is fabricated as a component of a neuromorphic convolutional neural network. Beyond the single transistor level, the long‐term potentiation and depression of synaptic weights are achieved at the array level, and a successful program‐inhibiting operation is demonstrated in the synaptic array, achieving a learning accuracy of 79.84% on the Canadian Institute for Advanced Research (CIFAR)‐10 dataset. Furthermore, an efficient self‐curing method is proposed to improve the endurance of the FeFET array by tenfold, utilizing the punch‐through current inherent to the device. Low‐frequency noise spectroscopy is employed to quantitatively evaluate the curing efficiency of the proposed self‐curing method. The results of this study provide a method to fabricate and operate reliable synaptic FeFET arrays, thereby paving the way for further development of ferroelectric‐based neuromorphic computing.