Wakeup-free and endurance-robust HfZrO2 (HZO) ferroelectric field-effect transistor (FeFET) was fabricated on a silicon-on-insulator substrate. After a high-pressure forming gas annealing as the last alloy step, the performance and endurance of the FeFETs were significantly improved by trap states reduction, polarization enhancement, and wake-up elimination. As the result, the FeFETs show superior endurance exceeding 1010 cycles and robust retention behavior at program/erase biases of ±3.5V and pulse width of 100 ns. These results indicate that appropriate thermal treatment for the interlayer and ferroelectric material could substantially improve FeFET performance and reliability.

In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA FET fabrication. Consequently, the thickness of channel and the interchannel space becomes variable depending on the NS width, since the etch time must be determined by the widest channel within a wafer. It results in a channel width dependence of gate work function, gate-to-drain capacitance, and channel interfacial property as well as the electrostatic gate controllability. The electrical characteristic behavior of stacked-GAAFETs induced by these effects was thoroughly investigated through process-based 3-D technology computer-aided design (TCAD) device simulation along with a transmission electron microscopy (TEM) and an energy-dispersive spectroscopy (EDS) analyses. The results confirm that width-dependent effects should be taken into account when fabricating and compact modeling the stacked-GAAFETs with various NS widths which are required for logic and static random access memory (SRAM) applications.

In this work, the low-frequency noise (LFN) characteristics of hafnium-zirconium oxide (HZO) ferroelectric field-effect transistors (FeFETs) with and without high-pressure forming gas annealing (HPA) treatment are investigated. The origin of $1/ {f}$ noise in the FeFET without HPA is changed from carrier number fluctuation to Hooge’s mobility fluctuation after wake-up due to the remote phonon scattering from the polarized HZO. Also, Hooge’s parameter is increased by the program/erase (P/E) cycling-induced stress. On the contrary, only the correlated mobility fluctuation is increased after the wake-up in the FeFET with HPA. Furthermore, the LFN of the FeFET with HPA shows robustness to P/E cycling-induced stress after the wake-up, showing superb endurance performance.

In this article, a 5-nm node two-stack nanosheet FET with a triple-k spacer structure representing three spacer regions consisting of two inner spacers (inner spacer 1 and inner spacer 2) formed by two atomic layer deposition (ALD) processes leveraging the inner spacer formation-process method and outer spacer process of stack gate-all-around (GAA) process is proposed. Material and structure optimization was performed to confirm the effects of each spacer regions. Inner spacer 1 has a direct effect on the channel extension region. However, the inner spacer 2 is not in direct contact with the channel extension region and the gate, thus confirming the relatively indirect effect. In addition, the material dependence of the outer spacer, formed between the gate and the side region of the channel where the field is concentrated, was confirmed. By comparing the optimized triple-k spacer structure with the fully nitride spacer, the improved dynamic performance, as well as the active power and static power, was identified.

Through a comparative analysis of gate-all-around field-effect transistors (GAAFETs) with the same layout footprint as FinFETs of 3-nm technology nodes, the effect of the tapered fin shape on device performance is determined using the 3-D technology computer-aided design (TCAD) simulation. Moreover, this comparative study presents the most optimal taper angle in terms of various device figures of merits (FoMs) for a standard supply voltage ( ${V}_{\text {DD}}$ ) of 0.7 V and a low ${V}_{\text {DD}}$ of 0.35 V. Since FinFET of sub-3 nm is most affected by the short-channel effect (SCE), the vertical shape with the best electrostatic control is advantageous for dc and ac performances. On the other hand, in the case of GAAFETs, such as nanowire (NW) and nanosheet (NS), although vertical fin is the lowest dc performance due to the smallest effective width, we confirmed the best ac results due to the impact of capacitance gain. Furthermore, we demonstrated that NWFET and NSFET with straight shapes could achieve more than the frequency gain of $2.2\times $ and $1.2\times $ at the same power, respectively, compared to FinFETs in low ${V}_{\text {DD}}$ operation.

We demonstrate a novel ferroelectric-gate field effect transistor with recessed channel (R-FeFET) to improve memory window (MW), program/erase speed, long-time retention, and endurance simultaneously. Based on technology computer-aided design (TCAD) simulations including calibrated ferroelectric material (FE) parameters, it is revealed that the polarization is enhanced by the larger electric field (e-field) across the FE compared to a conventional planar FeFET, resulting in the wider MW and the faster program/erase speed. Moreover, the endurance/retention of the R-FeFET is expected to be improved as the e-field across the SiO ₂ interlayer is significantly reduced.