A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.

This work presents a system level model of the clock jitter influence in certain types of continuous time sigma delta modulators. The model helps the design of such modulators by speeding up the simulations, predicting analytically the SNR degradation and providing a practical way to minimize the jitter sensitivity of the modulator. Simulations and theoretical developments are contrasted with measurements in a real chip.

This paper shows the operating principle and experimental results of a new continuous-time sigma-delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-mum CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.

Continuous physiological monitoring integrated within current wearable devices is a hot topic nowadays. Despite that, measuring physiological variables is still challenging due to intrinsic and extrinsic personal factors. This results in the need for smart, adjustable, and personalised sensing devices. Among the different physiological signals that can be measured, changes in skin conductance are extensively used in Affective Computing research. This measurement presents an unequivocal relationship with the sympathetic branch of the autonomous nervous system, which relates to emotional reactions. However, there is a lack of self-adjustable skin conductance sensors. This paper presents a novel skin conductance analog front-end to deal with individual physiological dynamics. We compared the performance of our system with other skin conductance sensor circuits presented in the literature. Moreover, the experimental results in this work come from the data collected in 47 women volunteers and are compared with the measurements with a reference physiological sensing system commonly used for validations. Finally, our system presents a competitive averaged sensitivity for a typical human EDA range compared to the current state-of-the-art solutions. Experimental results show that the system achieves an averaged sensitivity of up to 0.33 nS for a range 0 μS to 40 μS, with a relative error below 1% for fixed-resistance measurements, and a 0.94 median correlation coefficient when directly comparing with the reference sensor. Moreover, we extracted and analysed different physiological features in data from both sensors and obtained comparable results. Finally, this research is intended to boost the design and development of subject-independent and self-adjustable wearable sensors.

This paper proposes a new circuit-based approach to mitigate nonlinearity in open-loop ring-oscillator-based analog-to-digital converters (ADCs). The approach consists of driving a current-controlled oscillator (CCO) with several transconductors connected in parallel with different bias conditions. The current injected into the oscillator can then be properly sized to linearize the oscillator, performing the inverse current-to-frequency function. To evaluate the approach, a circuit example has been designed in a 65-nm CMOS process, leading to a more than 3-ENOB enhancement in simulation for a high-swing differential input voltage signal of 800-mV${}_{\mathrm{pp}}$, with considerable less complex design and lower power and expected area in comparison to state-of-the-art circuit based solutions. The architecture has also been checked against PVT and mismatch variations, proving to be highly robust, requiring only very simple calibration techniques. The solution is especially suitable for high-bandwidth (tens of MHz) medium-resolution applications (10–12 ENOBs), such as 5G or Internet-of-Things (IoT) devices.