This paper shows the operating principle and experimental results of a new continuous-time sigma-delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-mum CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.

High-resolution Sigma-Delta (ΣΔ) ADCs are increasingly used in portable medical applications for the measurement of biopotential signals. This paper presents the implementation and measurements of a novel ultra-low power low voltage multi-bit continuous-time sigma-delta (CT-ΣΔ) modulator, whose quantizer and feedback DACs operate in the time domain. Instead of the conventional flash quantizer and mismatch corrected multi-bit feedback DACs, a Dual-Slope (DS) quantizer and a Pulse-Width Modulated (PWM) DACs have been adopted in this design. The modulator has been implemented in a standard 0.18μm CMOS technology and features 83dB dynamic-range (DR) for a signal bandwidth of 256Hz. When clocked at 917kHz it consumes 13.3μW from a 1.4V supply.

Infrared imaging technology, used both to study deep-space bodies’ radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm² chip integrated in a standard 0.18-µm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping,analogcalibration,nordigitalcompensationtechnique. Whencoupledtoa2048×2048 IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW.

In this work, we analyze in depth multiple characteristic data of a representative population of radenv-ADCs (analog-to-digital converters able to operate under radiation). Selected ADCs behave without latch-up below 50 MeV·cm²/mg and are able to bear doses of ionizing radiation above 50 krad(Si). An exhaustive search of ADCs with radiation characterization data has been carried out throughout the literature. The obtained collection is analyzed and compared against the state of the art of scientific ADCs, which reached years ago the electrical performance that radenv-ADCs provide nowadays. In fact, for a given Nyquist sampling rate, radenv-ADCs require significantly more power to achieve lower effective resolution. The extracted performance patterns and conclusions from our study aim to serve as reference for new developments towards more efficient implementations. As tools for this purpose, we have conceived FOM${}_{TID}$ and FOM${}_{SET}$, two new figures of merit to compare radenv-ADCs that consider electrical and radiation performance.

This paper presents the system level design of a novel multi-bit Sigma-Delta (ΣΔ) ADC architecture that replaces the flash quantizer and mismatch corrected multi-bit DAC of a ΣΔ modulator by an integrating quantizer and a Pulse-Width Modulated DAC. This converter achieves the resolution of a multi-bit design using single-bit circuitry. The quantizer of this modulator is similar to a classical Dual-Slope integrating converter, but the charge residue in the integrator at the end of each conversion cycle is stored for the next conversion, providing first order noise shaping. As an example, the system level performance of a second-order multi-bit ¿¿ ADC using this new architecture has been evaluated. Also, circuit level specifications have been established, considering the most critical circuit non-idealities. The behavioral simulation results show that the ADC could achieve an ENOB = 13 bits in a signal bandwidth of 2 MHz using conventional CMOS technology, which could be suitable for wireless communication standards.