Low-voltage CMOS technologies pose new problems in the design of multibit continuous-time sigma-delta modulators. One of these problems is the implementation of the coarse quantizer with an array of voltage comparators. This work presents a novel architecture of multibit continuous-time sigma-delta modulator that employs a time encoding quantizer and irregular sampling instead of a flash analog-to-digital converter. The time-encoding quantizer is based in a modulated oscillator that produces a two-level signal. A digital decoder converts the binary signal into an irregularly sampled multibit signal that is interpolated and fed back into the loop filter of the sigma-delta modulator. This architecture is especially adequate for low-voltage technologies due to the absence of a resistive reference ladder in the quantizer and may permit a significant reduction of the complexity of the existing continuous-time sigma-delta modulators.

Presented is a new ADC topology based on an asynchronous PWM modulator followed by a VCO and a counter. The PWM modulator first encodes the analogue input into a binary waveform. Then, the VCO implements a multibit first-order noise shaping modulator, sampling and quantising the input signal encoded by the PWM modulator. With this architecture, the linearity of the whole converter is independent of the VCO linearity as the VCO is modulated by a two valued signal only. Proposed is a hardware implementation suitable for low power applications that does not require linear amplifiers.

The use of MEMS sensors has been increasing in recent years. To cover all the applications, many different readout circuits are needed. To reduce the cost and time to market, a generic capacitance-to-digital converter (CDC) seems to be the logical next step. This work presents a configurable CDC designed for capacitive MEMS sensors. The sensor is built with a bridge of MEMS, where some of them function with pressure. Then, the capacitive to digital conversion is realized using two steps. First, a switched-capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a self-oscillated noise-shaping integrating dual-slope (DS) converter is used to digitize this magnitude. The proposed converter uses time instead of amplitude resolution to generate a multibit digital output stream. In addition it performs noise shaping of the quantization error to reduce measurement time. This article shows the effectiveness of this method by measurements performed on a prototype, designed and fabricated using standard 0.13 µm CMOS technology. Experimental measurements show that the CDC achieves a resolution of 17 bits, with an effective area of 0.317 mm², which means a pressure resolution of 1 Pa, while consuming 146 µA from a 1.5 V power supply.

A noise-shaping Dual-Slope (DS) Capacitance-to-Digital Converter (CDC), specifically designed for interfacing capacitive MEMS sensors, is presented. In particular, this work proposes a design with a MEMS sensor built with a bridge of capacitors. In this bridge, some capacitors are function of the pressure in order to obtain a variation in the output of the bridge related with the change of pressure. Then, the capacitive to digital conversion is realized using two steps. First, a Switched-Capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a time domain noise-shaping Dual-Slope ADC is used to digitalize the magnitude of the capacitive bridge. The use of time instead of amplitude resolution leads to the following strengths: 1) intrinsically small sensitivity to temperature and process variations; 2) simplicity of trimming offset and gain to correct the sensor parameter spread; and 3) area and energy efficient implementation. The effectiveness of the method is demonstrated by measurements performed on a prototype, designed and fabricated using standard digital 0.13μm CMOS technology. Experimental results show that it achieves a resolution of 17-bit, which corresponds to a capacitive resolution of 5.4aF, while consuming only 146μA from a 1.5V power supply, with an effective area of 0.317mm².

This paper shows the operating principle and experimental results of a new continuous-time sigma-delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-mum CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.

High-resolution Sigma-Delta (ΣΔ) ADCs are increasingly used in portable medical applications for the measurement of biopotential signals. This paper presents the implementation and measurements of a novel ultra-low power low voltage multi-bit continuous-time sigma-delta (CT-ΣΔ) modulator, whose quantizer and feedback DACs operate in the time domain. Instead of the conventional flash quantizer and mismatch corrected multi-bit feedback DACs, a Dual-Slope (DS) quantizer and a Pulse-Width Modulated (PWM) DACs have been adopted in this design. The modulator has been implemented in a standard 0.18μm CMOS technology and features 83dB dynamic-range (DR) for a signal bandwidth of 256Hz. When clocked at 917kHz it consumes 13.3μW from a 1.4V supply.