We propose a universal and analytic step-by-step method to calculate the optimal 90° and 180° waveguide bends (L-bends and U-bends) in silicon-on-insulator photonics platform. This approach consists of first building an analytic model of loss per unit length as a function of radius of curvature and then using a variational optimization of the bending loss. It is shown that the shape of the optimal bends is ultimately determined either by the radiation loss of tight bends if the curvature of the bend is set to eliminate mode-mismatch losses or by the sidewall roughness loss if the radius of curvature is large. Numerical results from full wave simulations and comparison of the optimal bend with the Bezier, Euler, and Hybrid Euler-Circular bend are also provided to show the validity of our approach.

A detailed analysis of fundamental tradeoffs between ring radius and coupling gap size is presented to draw realistic borders of the possible design space for microring resonators (MRRs). The coupling coefficient for the ring-waveguide structure is estimated based on an integration of the nonuniform gap between the ring and the waveguide. Combined with the supermode analysis of two coupled waveguides, this approach is further expanded into a closed-form equation that describes the coupling strength. This equation permits to evaluate how the distance separating a waveguide from a ring resonator, and the ring radius, affect coupling. The effect of ring radius on the bending loss of the ring is furthermore modeled based on the measurements for silicon MRRs with different radii. These compact models for coupling and loss are subsequently used to derive the main optical properties of MRRs, such as 3-dB optical bandwidth, extinction ratio of resonance, and insertion loss, hence identifying the design space. Our results indicate that the design space for add-drop filters in a wavelength division multiplexed link is currently limited to 5-10 μm in radius and gap sizes ranging from 120 to 210 nm. The good agreement between the results from the proposed compact model for coupling and the numerical FDTD and experimental measurements indicate the application of our approach in realizing fast and efficient design space exploration of MRRs in silicon photonic interconnects.

Silicon photonics is an emerging paradigm for designing energy -efficient and high-performance communication backbone for manycore chips. This article presents a survey about designing photonic on-chip infrastructure.

Silicon photonic interconnect (SPI) is an attractive alternative for the power-hungry and low-bandwidth metallic interconnect in multiprocessor systems-on-chip (MPSoCs). When employing SPIs for wavelength-division multiplexing (WDM)-based applications, it is essential to precisely align the central wavelengths of different photonic devices (e.g., photonic switches) to achieve a reliable communication. However, SPIs are sensitive to fabrication nonuniformity (a.k.a. fabrication process variation), which results in wavelength mismatches between devices, and hence performance degradation in SPIs. This work presents a computationally efficient and accurate bottom-up approach to study the impact of fabrication process variations on passive silicon photonic devices and interconnects. We first model the impact of process variations at the component level (i.e., strip waveguides), then at the device level (i.e., add-drop filters and photonic switches), and finally at the system level (i.e., passive WDM-based SPIs). Numerical simulations are performed not only to evaluate the accuracy of our method, but also to demonstrate its high-computational efficiency. Furthermore, our study includes the design, fabrication, and analysis of several identical microresonators to demonstrate process variations in silicon photonics fabrication. The efficiency of our proposed method enables its application to large-scale passive SPIs in MPSoCs, where employing time-consuming numerical simulations is not feasible.

Silicon photonics (SiPh) technology has facilitated the deployment of integrated photonics across different application domains, from ultra-fast communication in Datacom applications to energy-efficient optical computation in emerging hardware accelerators for machine learning. More recently, the integration of SiPh and phase change materials has created a unique opportunity to realize adaptable, reconfigurable, and programmable photonic platforms. In particular, the nonvolatile programmability in phase change materials has made them a promising candidate for implementing photonic memory cells and architectures. Accordingly, photonic memory systems and even in-memory photonic computing paradigms are on the rise, especially given their potential for improving data access in electronic and photonic processors. However, there are still many challenges in the design and fabrication of phase-change photonic integrated circuits, which need to be addressed. This article presents a comprehensive survey on the recent advances and challenges for the integration of phase change materials with contemporary photonic devices while focusing on the photonic memory application. In particular, we explore phase-change photonic memory from the material level to the architecture level by presenting an overview of different material-level characteristics of phase change materials with their optical, electrical, and thermal properties as well as their integration into SiPh devices and photonic memory architectures and their application for in-memory photonic computing. We also present a comparison with electronic memory and discuss open research challenges that must be addressed to further advance phase-change photonic memory towards successful integration into emerging computing systems.

Silicon photonic microring resonators (MRRs) offer many advantages (e.g., compactness) and are often considered as the fundamental building block in optical interconnects and emerging photonic nanoprocessors and accelerators. Such devices are, however, sensitive to inevitable fabrication-process variations (FPVs) stemming from optical lithography imperfections. Consequently, silicon photonic integrated circuits (PICs) integrating MRRs often suffer from high power overhead required to compensate for the impact of FPVs on MRRs and, hence, realizing a reliable operation. On the other hand, the design space of MRRs is complex, including several correlated design parameters, thereby further exacerbating the design optimization of MRRs under FPVs. In this article, we present, for the first time, a comprehensive design-space exploration in passive and active MRRs under FPVs. In addition, we present design optimization in MRRs under FPVs while considering different performance metrics, such as tolerance to FPVs, quality factor, and 3-dB bandwidth in MRRs. Simulation and fabrication results obtained by measuring multiple fabricated MRRs designed using our design-space exploration demonstrate a significant 70% improvement on average in the MRRs’ tolerance to different FPVs. Furthermore, we apply the proposed design optimization to a case study of a wavelength-selective MRR-based demultiplexer, where we show considerable channel-spacing accuracy within 0.5 nm even when the MRRs are placed 500 $\mu \text{m}$ apart on a chip. Such improvements indicate the efficiency of the proposed design-space exploration and optimization to enable power-efficient and variation-resilient PICs and optical interconnects integrating MRRs.