Hydrothermal growth of ZnO nanorods has been widely used for the development of tactile sensors, with the aid of ZnO seed layers, favoring the growth of dense and vertically aligned nanorods. However, seed layers represent an additional fabrication step in the sensor design. In this study, a seedless hydrothermal growth of ZnO nanorods was carried out on Au-coated Si and polyimide substrates. The effects of both the Au morphology and the growth temperature on the characteristics of the nanorods were investigated, finding that smaller Au grains produced tilted rods, while larger grains provided vertical rods. Highly dense and high-aspect-ratio nanorods with hexagonal prismatic shape were obtained at 75 °C and 85 °C, while pyramid-like rods were grown when the temperature was set to 95 °C. Finite-element simulations demonstrated that prismatic rods produce higher voltage responses than the pyramid-shaped ones. A tactile sensor, with an active area of 1 cm², was fabricated on flexible polyimide substrate and embedding the nanorods forest in a polydimethylsiloxane matrix as a separation layer between the bottom and the top Au electrodes. The prototype showed clear responses upon applied loads of 2–4 N and vibrations over frequencies in the range of 20–800 Hz.

The channel length in vertical organic field effect transistors (VOFETs) is defined by the organic semiconductor (OSC) thin film thickness that can be in the nanometer range, which allows it to operate at low voltages, hence reducing the power consumption. The reduced channel length also leads to a much higher OFF-state current, and this can increase power leakage and deteriorate the performance, and hence, OFF-state current must be reduced using the modification of the VOFET structure. To address the high OFF-state current issue, modifications on the perforated source contact are explored using simulation studies. In geometrical modifications, the two structures viz. “on-dielectric” (OD) and “inside-channel” (IC) source contacts are compared, where the “OD” source contact is on the gate oxide layer, whereas “IC” source contact denotes an underlying OSC layer. The simulation results show that for optimized conditions, the “OD” source contact performed better than the “IC” source contact. The source contacts are further modified with insulating layers to improve the ON/OFF ratio and subthreshold swing (SS) in both geometries. The results suggest that reducing the thickness of the buried OSC layer in the “IC” contact configuration with top and side walls of source contact coated with insulator leads to the best performance having an ON/OFF ratio $\sim$ 10 $^{\text{8}}$ and SS 141 mV/decade. The improvements occur as the charge carrier injection takes place from the bottom side of the contact, and hence, the applied gate voltage can provide better control over the injection barrier due to the direct in-sight position of the source injection region.

Vertical organic field-effect transistors (VOFETs) can offer a short channel architecture that can further enhance the performance at low operating voltages, which makes it more viable for organic electronics applications. VOFETs can be prepared using low-cost techniques that reduce the high processing costs and can operate at high current densities and relatively high fRequencies. To further improve the performance, high current density, and operating frequency, the physics of charge carrier transport should be understood well with the simulation. The main problem with VOFET is the high off-current which is inevitable due to conduction from the source to the drain contact. Many efforts have been made to reduce the off-state current by the addition of an insulating layer on top of the source electrode, which further increases the processing complexity and cost of fabrication. Simulations based on device geometry, contact barriers, and organic semiconductor parameters are carried out to study the charge carrier transport in VOFET. The simulation results show that the most important factor, to enhance the performance is the device geometry or architecture, which requires a specific fill factor, a ratio of the exposed gate dielectric width to the total width of the device with the source electrode. The simulation results also show a different type of working physics of the basic VOFET architecture where the On/Off ratio and subthreshold swing are largely dependent on the initial negative gate field instead of the accumulated charge carriers at positive gate fields. Optimized VOFET architecture is then simulated for variation in contact barrier and semiconductor properties, which show further enhancement in performance.

Poly[2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2- b ]thiophene] (PBTTT-C14) based two-terminal devices with hexagonal bottom contact geometry show resistive switching memory from low resistive state (LRS) to high resistive state (HRS).

Vertical organic field effect transistors (VOFETs) are of paramount importance due to their fast switching speed, low power consumption, and higher density on a chip compared to lateral OFETs. The low charge carrier mobility in organic semiconductors and longer channel lengths in lateral OFETs lead to higher operating voltages. The channel length in VOFETs can be less than 100 nm which reduces the size of the channel and hence the operating voltages. Another important factor in the operation of VOFETs is the thickness and width of the source electrode. The channel length, source electrode thickness and width sets the miniaturization limit of the VOFETs. The graphene monolayer can be exploited as a source electrode due to its thinness, high carrier mobility, and metallic behaviors. However, for better gate modulation, perforations in the source material are desired. Here, we simulate the VOFET having perforated graphene monolayer as a source electrode and n-type organic semiconductor N, N′-dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C8) as an active channel material, while aluminum as a drain electrode to predict the best-miniaturized device. The miniaturization limit of such a VOFET has a limit to the gate opening/perforation in which the minimum source width is 10 nm, as in the sub 10 nm range graphene starts behaving like a semiconductor. The subthreshold swing, deduced from the drain current (J _D) versus gate voltage (V _G) graph, advocates the limit of the organic semiconductor height/channel length to 50 nm, while 50 nm for the gate.